View M58CR064C_165639.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M58CR064C, M58CR064D M58CR064P, M58CR064Q
64 Mbit (4Mb x 16, Dual Bank, Burst ) 1.8V Supply Flash Memory
FEATURES SUMMARY s SUPPLY VOLTAGE - VDD = 1.65V to 2V for Program, Erase and Read - VDDQ = 1.65V to 3.3V for I/O Buffers - VPP = 12V for fast Program (optional)
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Figure 1. Package
SYNCHRONOUS / ASYNCHRONOUS READ - Synchronous Burst Read mode : 54MHz - Asynchronous/ Synchronous Page Read mode - Random Access: 85, 90, 100, 120ns
FBGA
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PROGRAMMING TIME - 10s by Word typical - Double/Quadruple Word Program option
TFBGA56 (ZB) 6.5 x 10mm
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MEMORY BLOCKS - Dual Bank Memory Array: 16/48 Mbit - Parameter Blocks (Top or Bottom location)
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DUAL OPERATIONS - Program Erase in one Bank while Read in other - No delay between Read and Write operations
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ELECTRONIC SIGNATURE - Manufacturer Code: 20h - Top Device Code, M58CR064C: 88CAh - Bottom Device Code, M58CR064D: 88CBh - Top Device Code, M58CR064P: 8801h - Bottom Device Code, M58CR064Q: 8802h
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BLOCK LOCKING - All blocks locked at Power up - Any combination of blocks can be locked - WP for Block Lock-Down
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SECURITY - 128 bit user programmable OTP cells - 64 bit unique device number - One parameter block permanently lockable
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COMMON FLASH INTERFACE (CFI) 100,000 PROGRAM/ERASE CYCLES per BLOCK
June 2003
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2. Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Address Inputs (A0-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Reset/Power-Down (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Latch Enable (L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Clock (K).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Wait (WAIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VDD Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VDDQ Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VPP Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VSSQ Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Address Latch.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 3. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 4. Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 COMMAND INTERFACE - STANDARD COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Read Array Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Read Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Read CFI Query Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Clear Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
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Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Set Configuration Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Block Lock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Block Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Block Lock-Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 5. Standard Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 6. Electronic Signature Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 5. Security Block and Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 COMMAND INTERFACE - FACTORY PROGRAM COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . 18 Bank Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Double Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Quadruple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 7. Factory Program Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Program/Erase Controller Status Bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Erase Suspend Status Bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Erase Status Bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Program Status Bit (SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 VPP Status Bit (SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Program Suspend Status Bit (SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Block Protection Status Bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Reserved Bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 8. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 CONFIGURATION REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Read Select Bit (CR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 X-Latency Bits (CR13-CR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Power-Down Bit (CR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Wait Configuration Bit (CR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Burst Type Bit (CR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Valid Clock Edge Bit (CR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Wrap Burst Bit (CR3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Burst length Bits (CR2-CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 9. Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 10. Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 6. X-Latency and Data Output Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 7. Wait Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 READ MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Asynchronous Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Synchronous Burst Read Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Single Synchronous Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 11. Dual Operations Allowed In Other Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 12. Dual Operations Allowed In Same Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 BLOCK LOCKING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Reading a Block's Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Unlocked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Lock-Down State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 13. Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 14. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 30 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 15. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 16. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 8. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 9. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 17. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 18. DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 19. DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 10. Asynchronous Random Access Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 11. Asynchronous Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 20. Asynchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 12. Synchronous Burst Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 13. Single Synchronous Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 21. Synchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 14. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 22. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 15. Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 23. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 16. Reset and Power-up AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 24. Reset and Power-up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 17. TFBGA56 6.5x10mm - 8x7 ball array, 0.75 mm pitch, Bottom View Package Outline. . 46 Table 25. TFBGA56 6.5x10mm - 8x7 ball array, 0.75 mm pitch, Package Mechanical Data . . . . . 46 Figure 18. TFBGA56 Daisy Chain - Package Connections (Top view through package) . . . . . . . . 47 Figure 19. TFBGA56 Daisy Chain - PCB Connection Proposal (Top view through package). . . . . 48 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 26. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
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Table 27. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 APPENDIX A. BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 28. Top Boot Block Addresses, M58CR064C, M58CR064P . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 29. Bottom Boot Block Addresses, M58CR064D, M58CR064Q . . . . . . . . . . . . . . . . . . . . . . 52 APPENDIX B. COMMON FLASH INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 30. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 31. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 32. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 33. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 34. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 35. Burst Read Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 APPENDIX C. FLOWCHARTS AND PSEUDO CODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 20. Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 21. Double Word Program Flowchart and Pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 22. Quadruple Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 23. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 61 Figure 24. Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 25. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 26. Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 27. Protection Register Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 65 APPENDIX D. COMMAND INTERFACE STATE TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 36. Command Interface States - Lock table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 37. Command Interface States - Modify Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 38. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
SUMMARY DESCRIPTION The M58CR064 is a 64 Mbit (4Mbit x16) non-volatile Flash memory that may be erased electrically at block level and programmed in-system on a Word-by-Word basis using a 1.65V to 2V VDD supply for the circuitry and a 1.65V to 3.3V VDDQ supply for the Input/Output pins. An optional 12V VPP power supply is provided to speed up customer programming. In M58CR064C and M58CR064D the VPP pin can also be used as a control pin to provide absolute protection against program or erase. In M58CR064P and M58CR064Q this feature is disabled. The device features an asymmetrical block architecture. M58CR064 has an array of 135 blocks, and is divided into two banks, Banks A and B. The Dual Bank Architecture allows Dual Operations, while programming or erasing in one bank, Read operations are possible in the other bank. Only one bank at a time is allowed to be in Program or Erase mode. It is possible to perform burst reads that cross bank boundaries. The bank architecture is summarized in Table 2, and the memory maps are shown in Figure 4. The Parameter Blocks are located at the top of the memory address space for the M58CR064C and M58CR064P, and at the bottom for the M58CR064D and M58CR064Q. Each block can be erased separately. Erase can be suspended, in order to perform program in any other block, and then resumed. Program can be suspended to read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles using the supply voltage V DD. Program and Erase commands are written to the Command Interface of the memory. An internal Program/Erase Controller takes care of the timings necessary for program and erase operations.
The end of a program or erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC standards. The device supports synchronous burst read and asynchronous read from all blocks of the memory array; at power-up the device is configured for asynchronous read. In synchronous burst mode, data is output on each clock cycle at frequencies of up to 54MHz. The M58CR064 features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any accidental programming or erasure. In M58CR064C and M58CR064D there is an additional hardware protection against program and erase. When VPP VPPLK all blocks are protected against program or erase. All blocks are locked at Power- Up. The device includes a Protection Register and a Security Block to increase the protection of a system's design. The Protection Register is divided into two segments: a 64 bit segment containing a unique device number written by ST, and a 128 bit segment One-Time-Programmable (OTP) by the user. The user programmable segment can be permanently protected. The Security Block, parameter block 0, can be permanently protected by the user. Figure 5, shows the Security Block and Protection Register Memory Map. The memory is offered in a TFBGA56, 6.5 x 10mm, 0.75 mm ball pitch package and is supplied with all the bits erased (set to '1').
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Figure 2. Logic Diagram Table 1. Signal Names
A0-A21 DQ0-DQ15 Address Inputs Data Input/Outputs, Command Inputs Chip Enable Output Enable Write Enable Reset/Power-Down Write Protect Clock Latch Enable Wait Supply Voltage Supply Voltage for Input/Output Buffers Optional Supply Voltage for Fast Program & Erase Ground Ground Input/Output Supply Not Connected Internally
VDD VDDQ VPP 22 A0-A21 W E G RP WP L K M58CR064C M58CR064D M58CR064P M58CR064Q WAIT 16 DQ0-DQ15
E G W RP WP K L WAIT VDD VDDQ VPP
VSS
VSSQ
AI90000
VSS VSSQ NC
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Figure 3. TFBGA Connections (Top view through package)
1 2 3 4 5 6 7 8
A
A11
A8
VSS
VDD
VPP
A18
A6
A4
B
A12
A9
A20
K
RP
A17
A5
A3
C
A13
A10
A21
L
W
A19
A7
A2
D
A15
A14
WAIT
A16
DQ12
WP
NC
A1
E
VDDQ
DQ15
DQ6
DQ4
DQ2
DQ1
E
A0
F
VSS
DQ14
DQ13
DQ11
DQ10
DQ9
DQ0
G
G
DQ7
VSSQ
DQ5
VDD
DQ3
VDDQ
DQ8
VSSQ
AI90001
Table 2. Bank Architecture
Bank Size Bank A Bank B 16 Mbit 48 Mbit Parameter Blocks 8 blocks of 4 KWord Main Blocks 31 blocks of 32 KWord 96 blocks of 32 KWord
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Figure 4. Memory Map
Top Boot Block Address lines A21-A0 000000h 007FFFh Bank B 512 Kbit or 32 KWord Total of 96 Main Blocks (bottom bank) 2F8000h 2FFFFFh 300000h 307FFFh 007000h Bank A 512 Kbit or 32 KWord Total of 31 Main Blocks (top bank) 3F0000h Bank A 3F7FFFh 3F8000h 3F8FFFh 512 Kbit or 32 KWord 64 Kbit or 4 KWord Total of 8 Parameter Blocks (top bank) 3FF000h 3FFFFFh 64 Kbit or 4 KWord 0F8000h 0FFFFFh 100000h 107FFFh Bank B 512 Kbit or 32 KWord 512 Kbit or 32 KWord Total of 96 Main Blocks (top bank) 3F8000h 3FFFFFh 512 Kbit or 32 KWord 007FFFh 008000h 00FFFFh 000000h 000FFFh Bottom Boot Block Address lines A21-A0 64 Kbit or 4 KWord Total of 8 Parameter Blocks (bottom bank) 64 Kbit or 4 KWord 512 Kbit or 32 KWord Total of 31 Main Blocks (bottom bank)
512 Kbit or 32 KWord
AI90002
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
SIGNAL DESCRIPTIONS See Figure 2 Logic Diagram and Table 1,Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A21). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. Data Input/Output (DQ0-DQ15). The Data I/O outputs the data stored at the selected address during a Bus Read operation or inputs a command or the data to be programmed during a Bus Write operation. Chip Enable (E). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at VILand Reset/Power-Down is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high impedance and the power consumption is reduced to the stand-by level. Output Enable (G). The Output Enable controls the outputs during the Bus Read operation of the memory. Write Enable (W). The Write Enable controls the Bus Write operation of the memory's Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first. Write Protect (WP). Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at VIL, the LockDown is enabled and the protection status of the Locked-Down blocks cannot be changed. When Write Protect is at VIH, the Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (refer to Table 13, Lock Status). Reset/Power-Down (RP). The Reset/PowerDown input provides a hardware reset of the memory, and/or Power-Down functions, depending on the Configuration Register status. When Reset/ Power-Down is at VIL, the memory is in reset mode: the outputs are high impedance and if the Power-Down function is enabled the current consumption is reduced to the Reset Supply Current IDD2. Refer to Table 18, DC Characteristics - Currents for the value of IDD2. After Reset all blocks are in the Locked state and the Configuration Register is reset. When Reset/Power-Down is at VIH, the device is in normal operation. Exiting reset mode the device enters asynchronous read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset/Power-Down pin can be interfaced with 3V logic without any additional circuitry. It can be
tied to V RPH (refer to Table 19, DC Characteristics). Latch Enable (L). Latch Enable latches the address bits on its rising edge. The address latch is transparent when Latch Enable is at VIL and it is inhibited when Latch Enable is at VIH. Latch Enable can be kept Low (also at board level) when the Latch Enable function is not required or supported. Clock (K). The clock input synchronizes the memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge (rising or falling, according to the configuration settings) when Latch Enable is at VIL. Clock is don't care during asynchronous read and in write operations. Wait (WAIT). Wait is an output signal used during synchronous read to indicate whether the data on the output bus are valid. This output is high impedance when Chip Enable or Output Enable are at VIH or Reset/Power-Down is at V IL. It can be configured to be active during the wait cycle or one clock cycle in advance. VDD Supply Voltage. VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (Read, Program and Erase). VDDQ Supply Voltage. VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered independently from VDD. VDDQ can be tied to VDD or can use a separate supply. VPP Program Supply Voltage. VPP is both a control input and a power supply pin. In M58CR064C/D the two functions are selected by the voltage range applied to the pin. In the M58CR064P/Q the control feature is disabled. In M58CR064C/D if VPP is kept in a low voltage range (0V to VDDQ) V PP is seen as a control input. In this case a voltage lower than VPPLK gives an absolute protection against program or erase, while VPP > VPP1 enables these functions (see Tables 18 and 19, DC Characteristics for the relevant values). VPP is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. If V PP is in the range of VPPH it acts as a power supply pin. In this condition VPP must be stable until the Program/Erase algorithm is completed. VSS Ground. VSS ground is the reference for the core supply. It must be connected to the system ground. VSSQ Ground. VSSQ ground is the reference for the input/output circuitry driven by V DDQ. VSSQ must be connected to V SS
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Note: Each device in a system should have VDD, VDDQ and V PP decoupled with a 0.1F ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 9, AC Measurement Load Circuit. The PCB track widths should be sufficient to carry the required V PP program and erase currents.
BUS OPERATIONS There are six standard bus operations that control the device. These are Bus Read, Bus Write, Address Latch, Output Disable, Standby and Reset. See Table 3, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect Bus Write operations. Bus Read. Bus Read operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the Common Flash Interface. Both Chip Enable and Output Enable must be at V IL in order to perform a read operation. The Chip Enable input should be used to enable the device. Output Enable should be used to gate data onto the output. The data read depends on the previous command written to the memory (see Command Interface section). Refer to the Read AC Waveform figures and Characteristics tables in the DC and AC Parameters section for details of when the output becomes valid. Bus Write. Bus Write operations write Commands to the memory or latch Input Data to be programmed. A bus write operation is initiated when Chip Enable and Write Enable are at VIL with Output Enable at VIH. Commands, Input Data and Addresses are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. The addresses can also be latched prior to the write operation by toggling Latch Enable. In this case
the Latch Enable should be tied to VIH during the bus write operation. See Figures 14 and 15, Write AC Waveforms, and Tables 22 and 23, Write AC Characteristics, for details of the timing requirements. Address Latch. Address latch operations input valid addresses. Both Chip enable and Latch Enable must be at V IL during address latch operations. The addresses are latched on the rising edge of Latch Enable. Output Disable. The outputs are high impedance when the Output Enable is at VIH. Standby. Standby disables most of the internal circuitry allowing a substantial reduction of the current consumption. The memory is in stand-by when Chip Enable and Reset/Power-Down are at VIH. The power consumption is reduced to the stand-by level and the outputs are set to high impedance, independently from the Output Enable or Write Enable inputs. If Chip Enable switches to VIH during a program or erase operation, the device enters Standby mode when finished. Reset. During Reset mode the memory is deselected and the outputs are high impedance. The memory is in Reset mode when Reset/PowerDown is at VIL. The power consumption is reduced to the Standby level, independently from the Chip Enable, Output Enable or Write Enable inputs. If Reset is pulled to VSS during a Program or Erase, this operation is aborted and the memory content is no longer valid.
Table 3. Bus Operations
Operation Bus Read Bus Write Address Latch Output Disable Standby Reset E VIL VIL VIL VIL VIH X G VIL VIH X VIH X X W VIH VIL VIH VIH X X L VIL(2) VIL(2) VIL X X X RP VIH VIH VIH VIH VIH VIL Hi-Z Hi-Z Hi-Z Hi-Z WAIT DQ15-DQ0 Data Output Data Input Data Output or Hi-Z (3) Hi-Z Hi-Z Hi-Z
Note: 1. X = Don't care. 2. L can be tied to VIH if the valid address has been previously latched. 3. Depends on G.
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
COMMAND INTERFACE All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. An internal Program/Erase Controller handles all timings and verifies the correct execution of the Program and Erase commands. The Program/Erase Controller provides a Status Register whose output may be read at any time to monitor the progress or the result of the operation. The Command Interface is reset to read mode when power is first applied, when exiting from Reset or whenever V DD is lower than VLKO . Command sequences must be followed exactly. Any invalid combination of commands will reset the device to read mode. Refer to Table 4, Command Codes and Appendix D, Tables 36 and 37, Command Interface States Modify and Lock Tables, for a summary of the Command Interface. The Command Interface is split into two types of commands: Standard commands and Factory Program commands. The following sections explain in detail how to perform each command.
Table 4. Command Codes
Hex Code 01h 03h 10h 20h 2Fh 30h 40h 50h 55h 60h 70h 80h 90h 98h B0h C0h D0h FFh Command Block Lock Confirm Set Configuration Register Confirm Alternative Program Setup Block Erase Setup Block Lock-Down Confirm Double Word Program Setup Program Setup Clear Status Register Quadruple Word Program Setup Block Lock Setup, Block Unlock Setup, Block Lock Down Setup and Set Configuration Register Setup Read Status Register Bank Erase Setup Read Electronic Signature Read CFI Query Program/Erase Suspend Protection Register Program Program/Erase Resume, Block Erase Confirm, Bank Erase Confirm, Block Unlock Confirm Read Array
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
COMMAND INTERFACE - STANDARD COMMANDS The following commands are the basic commands Read CFI Query Command used to read, write to and configure the device. The Read CFI Query command is used to read Refer to Table 5, Standard Commands, in condata from the Common Flash Interface (CFI) junction with the following text descriptions. memory area located in the bottom bank. The Read Array Command Read CFI Query Command consists of one Bus Write cycle, to an address within the bottom bank. The Read Array command returns the addressed Once the command is issued subsequent Bus bank to Read Array mode. One Bus Write cycle is Read operations in the same bank read from the required to issue the Read Array command and reCommon Flash Interface. turn the addressed bank to Read Array mode. Subsequent read operations will read the adIf a Read CFI Query command is issued in a bank dressed location and output the data. A Read Arthat is executing a Program or Erase operation the ray command can be issued in one bank while bank will go into Read Status Register mode, subprogramming or erasing in the other bank. Howevsequent Bus Read cycles will output the Status er if a Read Array command is issued to a bank Register and the Program/Erase controller will currently executing a Program or Erase operation continue to Program or Erase in the background. the command will be ignored. When the Program or Erase operation has finished the device will enter Read CFI Query mode. Read Status Register Command This mode supports asynchronous or single synA Bank's Status Register indicates when a Prochronous reads only, it does not support page gram or Erase operation is complete and the sucmode or synchronous burst reads. cess or failure of operation itself. Issue a Read Status Register command to read the Status RegThe status of the other banks is not affected by the ister content of the addressed Bank. The Read command (see Table 11). After issuing a Read Status Register command can be issued at any CFI Query command, a Read Array command time, even during Program or Erase operations. should be issued to the addressed bank to return the bank to read mode. The following Bus Read operations output the content of the Status Register of the addressed bank. See Appendix B, Common Flash Interface, Tables The Status Register is latched on the falling edge 30, 31, 32, 33, 34 and 35 for details on the inforof E or G signals, and can be read until E or G remation contained in the Common Flash Interface turns to VIH. Either E or G must be toggled to upmemory area. date the latched data. See Table 8 for the Clear Status Register Command description of the Status Register Bits. This mode The Clear Status Register command can be used supports asynchronous or single synchronous to reset (set to `0') error bits SR1, SR3, SR4 and reads only. SR5 in the Status Register of the addressed bank. Read Electronic Signature Command One bus write cycle is required to issue the Clear The Read Electronic Signature command reads Status Register command. After the Clear Status the Manufacturer and Device Codes, the Block Register command the bank returns to Read Array Locking Status, the Protection Register, and the mode. Configuration Register. The error bits in the Status Register do not autoThe Read Electronic Signature command consists matically return to `0' when a new command is isof one write cycle to an address within the bottom sued. The error bits in the Status Register should bank. A subsequent read operation in the address be cleared before attempting a new Program or of the bottom bank will output the Manufacturer Erase command. Code, the Device Code, the protection Status of Block Erase Command Blocks of the bottom bank, the Die Revision Code, The Block Erase command can be used to erase the Protection Register, or the Read Configuration a block. It sets all the bits within the selected block Register (see Table 6). to '1'. All previous data in the block is lost. If the If the first write cycle of Read Electronic Signature block is protected then the Erase operation will command is issued to an address within the top abort, the data in the block will not be changed and bank, a subsequent read operation in an address the Status Register will output the error. The Block of the top bank will output the protection Status of Erase command can be issued at any moment, reblocks of the top bank. The status of the other gardless of whether the block has been probank is not affected by the command (see Table grammed or not. 11). This mode supports asynchronous or single Two Bus Write cycles are required to issue the synchronous reads only, it does not support page command. mode or synchronous burst reads. s The first bus cycle sets up the Erase command.
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
The second latches the block address in the internal state machine and starts the Program/ Erase Controller. If the second bus cycle is not Write Erase Confirm (D0h), Status Register bits SR4 and SR5 are set and the command aborts. Erase aborts if Reset turns to VIL. As data integrity cannot be guaranteed when the Erase operation is aborted, the block must be erased again. Once the command is issued the device outputs the Status Register data when any address within the bank is read. At the end of the operation the bank will remain in Read Status Register mode until a Read Array, Read CFI Query or Read Electronic Signature command is issued. During Erase operations the bank containing the block being erased will only accept the Read Status Register and the Program/Erase Suspend command, all other commands will be ignored. Refer to Dual Operations section for detailed information about simultaneous operations allowed in banks not being erased. Typical Erase times are given in Table 14, Program, Erase Times and Program/Erase Endurance Cycles. See Appendix C, Figure 24, Block Erase Flowchart and Pseudo Code, for a suggested flowchart for using the Block Erase command. Program Command The memory array can be programmed word-byword. Only one Word in one bank can be programmed at any one time. Two bus write cycles are required to issue the Program Command. s The first bus cycle sets up the Program command. s The second latches the Address and the Data to be written and starts the Program/Erase Controller. After programming has started, read operations in the bank being programmed output the Status Register content. During Program operations the bank being programmed will only accept the Read Status Register and the Program/Erase Suspend command. Refer to Dual Operations section for detailed information about simultaneous operations allowed in banks not being programmed. Typical Program times are given in Table 14, Program, Erase Times and Program/Erase Endurance Cycles. Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the memory location must be reprogrammed. See Appendix C, Figure 20, Program Flowchart and Pseudo Code, for the flowchart for using the Program command.
s
Program/Erase Suspend Command The Program/Erase Suspend command is used to pause a Program or Block Erase operation. A Bank Erase operation cannot be suspended. One bus write cycle is required to issue the Program/Erase Suspend command. Once the Program/Erase Controller has paused bits SR7, SR6 and/ or SR2 of the Status Register will be set to `1'. The command must be addressed to the bank containing the Program or Erase operation. During Program/Erase Suspend the Command Interface will accept the Program/Erase Resume, Read Array (cannot read the suspended block), Read Status Register, Read Electronic Signature and Read CFI Query commands. Additionally, if the suspend operation was Erase then the Clear status Register, Program, Block Lock, Block LockDown or Protection Program commands will also be accepted. The block being erased may be protected by issuing the Block Lock, Block LockDown or Protection Register Program commands. Only the blocks not being erased may be read or programmed correctly. When the Program/Erase Resume command is issued the operation will complete. Refer to the Dual Operations section for detailed information about simultaneous operations allowed during Program/Erase Suspend. During a Program/Erase Suspend, the device can be placed in standby mode by taking Chip Enable to VIH. Program/Erase is aborted if Reset turns to VIL. See Appendix C, Figure 23, Program Suspend & Resume Flowchart and Pseudo Code, and Figure 25, Erase Suspend & Resume Flowchart and Pseudo Code for flowcharts for using the Program/ Erase Suspend command. Program/Erase Resume Command The Program/Erase Resume command can be used to restart the Program/Erase Controller after a Program/Erase Suspend command has paused it. One Bus Write cycle is required to issue the command. The command must be written to the bank containing the Program or Erase Suspend. The Program/Erase Resume command changes the read mode of the target bank to Read Status Register mode. If a Program command is issued during a Block Erase Suspend, then the erase cannot be resumed until the programming operation has completed. It is possible to accumulate suspend operations. For example: suspend an erase operation, start a programming operation, suspend the programming operation then read the array. See Appendix C, Figure 23, Program Suspend & Resume Flowchart and Pseudo Code, and Figure 25, Erase Suspend & Resume Flowchart and Pseudo
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Code for flowcharts for using the Program/Erase Resume command. Protection Register Program Command The Protection Register Program command is used to Program the 128 bit user One-Time-Programmable (OTP) segment of the Protection Register. The segment is programmed 16 bits at a time. When shipped all bits in the segment are set to `1'. The user can only program the bits to `0'. Two write cycles are required to issue the Protection Register Program command. s The first bus cycle sets up the Protection Register Program command. s The second latches the Address and the Data to be written to the Protection Register and starts the Program/Erase Controller. Read operations output the Status Register content after the programming has started. The segment can be protected by programming bit 1 of the Protection Lock Register. Bit 1 of the Protection Lock Register also protects bit 2 of the Protection Lock Register. Programming bit 2 of the Protection Lock Register will result in a permanent protection of Parameter Block #0 (see Figure 5, Security Block and Protection Register Memory Map). Attempting to program a previously protected Protection Register will result in a Status Register error. The protection of the Protection Register and/or the Security Block is not reversible. The Protection Register Program cannot be suspended. See Appendix C, Figure 27, Protection Register Program Flowchart and Pseudo Code, for a flowchart for using the Protection Register Program command. Set Configuration Register Command. The Set Configuration Register command is used to write a new value to the Configuration Control Register which defines the burst length, type, X latency, Synchronous/Asynchronous Read mode and the valid Clock edge configuration. Two Bus Write cycles are required to issue the Set Configuration Register command. s The first cycle writes the setup command and the address corresponding to the Configuration Register content. s The second cycle writes the Configuration Register data and the confirm command. Once the command is issued the memory returns to Read mode. The value for the Configuration Register is always presented on A0-A15. CR0 is on A0, CR1 on A1, etc.; the other address bits are ignored. Block Lock Command The Block Lock command is used to lock a block and prevent Program or Erase operations from changing the data in it. All blocks are locked at power-up or reset. Two Bus Write cycles are required to issue the Block Lock command. s The first bus cycle sets up the Block Lock command. s The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Table. 13 shows the Lock Status after issuing a Block Lock command. The Block Lock bits are volatile, once set they remain set until a hardware reset or power-down/ power-up. They are cleared by a Block Unlock command. Refer to the section, Block Locking, for a detailed explanation. See Appendix C, Figure 26, Locking Operations Flowchart and Pseudo Code, for a flowchart for using the Lock command. Block Unlock Command The Block Unlock command is used to unlock a block, allowing the block to be programmed or erased. Two Bus Write cycles are required to issue the Block Unlock command. s The first bus cycle sets up the Block Unlock command. s The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Table 13 shows the protection status after issuing a Block Unlock command. Refer to the section, Block Locking, for a detailed explanation and Appendix C, Figure 26, Locking Operations Flowchart and Pseudo Code, for a flowchart for using the Unlock command. Block Lock-Down Command A locked or unlocked block can be locked-down by issuing the Block Lock-Down command. A lockeddown block cannot be programmed or erased, or have its protection status changed when WP is low, VIL. When WP is high, VIH, the Lock-Down function is disabled and the locked blocks can be individually unlocked by the Block Unlock command. Two Bus Write cycles are required to issue the Block Lock-Down command. s The first bus cycle sets up the Block Lock command. s The second Bus Write cycle latches the block address.
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The lock status can be monitored for each block using the Read Electronic Signature command. Locked-Down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. Table. 13 shows the Lock Status afTable 5. Standard Commands
Commands Cycles Bus Operations 1st Cycle Op.
Write Write Write Write Write Write Write Write Write Write Write Write Write Write
ter issuing a Block Lock-Down command. Refer to the section, Block Locking, for a detailed explanation and Appendix C, Figure 26, Locking Operations Flowchart and Pseudo Code, for a flowchart for using the Lock-Down command.
2nd Cycle Data
FFh 70h 90h 98h 50h 20h 40h or 10h B0h D0h C0h 60h 60h 60h 60h Write Write Write Write Write Write Write BA WA D0h PD
Add
BKA BKA BBKA or BKA(3) BBKA BKA BKA BKA BKA BKA PRA CRD BKA BKA BKA
Op.
Read Read Read Read
Add
WA BKA(2) BBKA or BKA(2,3) BBKA (2)
Data
RD SRD ESD(3) QD
Read Array Read Status Register Read Electronic Signature Read CFI Query Clear Status Register Block Erase Program Program/Erase Suspend Program/Erase Resume Protection Register Program Set Configuration Register Block Lock Block Unlock Block Lock-Down
1+ 1+ 1+ 1+ 1 2 2 1 1 2 2 2 2 2
PRA CRD BA BA BA
PRD 03h 01h D0h 2Fh
Note: 1. X = Don't Care, WA=Word Address in targeted bank, RD=Read Data, SRD=Status Register Data, ESD=Electronic Signature Data, QD=Query Data, BA=Block Address, BKA= Bank Address, BBKA= Bottom Bank Address, PD=Program Data, PRA=Protection Register Address, PRD=Protection Register Data, CRD=Configuration Register Data. 2. Must be same bank as in the first cycle. The signature addresses are listed in Table 6. 3. When addressed to a block in the Top Bank, reads Block Protection data only.
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Table 6. Electronic Signature Codes
Code Manufacturer Code Top (M58CR064C) Bottom (M58CR064D) Device Code Top (M58CR064P) Bottom (M58CR064Q) Lock Unlocked Block Protection Locked and Locked-Down Unlocked and Locked-Down Reserved Configuration Register ST Factory Default Security Block Permanently Locked Protection Register Lock OTP Area Permanently Locked Security Block and OTP Area Permanently Locked Bottom Bank Address + 81 Bottom Bank Address + 84 Protection Register Bottom Bank Address + 85 Bottom Bank Address + 8C
Note: CR=Configuration Register.
Address (h) Bottom Bank Address + 00
Data (h) 0020 88CA 88CB
Bottom Bank Address + 01 8801 8802 0001 0000 Block Address + 02 0003 0002 Bottom Bank Address + 03 Bottom Bank Address + 05 Reserved CR xx06 xx02 Bottom Bank Address + 80 xx04 xx00 Unique Device Number OTP Area
Figure 5. Security Block and Protection Register Memory Map
PROTECTION REGISTER 8Ch SECURITY BLOCK 85h 84h Parameter Block # 0 81h 80h Protection Register Lock 2 1 0 Unique device number User Programmable OTP
AI06181
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COMMAND INTERFACE - FACTORY PROGRAM COMMANDS The Factory Program commands are used to Double Word Program Command speed up programming. They require V PP to be at The Double Word Program command improves VPPH except for the Bank Erase command which the programming throughput by writing a page of also operates at VPP = VDD. Refer to Table 7, Factwo adjacent words in parallel. The two words tory Program Commands, in conjunction with the must differ only for the address A0. following text descriptions. Programming should not be attempted when VPP Bank Erase Command is not at VPPH. The command can be executed if VPP is below VPPH but the result is not guaranteed. The Bank Erase command can be used to erase a bank. It sets all the bits within the selected bank to Three bus write cycles are necessary to issue the '1'. All previous data in the bank is lost. The Bank Double Word Program command. Erase command will ignore any protected blocks s The first bus cycle sets up the Double Word within the bank. If all blocks in the bank are proProgram Command. tected then the Bank Erase operation will abort s The second bus cycle latches the Address and and the data in the bank will not be changed. The the Data of the first word to be written. Status Register will not output any error. s The third bus cycle latches the Address and the Bank Erase operations can be performed at both Data of the second word to be written and starts VPP = VPPH and V PP = VDD. the Program/Erase Controller. Two Bus Write cycles are required to issue the Read operations in the bank being programmed command. output the Status Register content after the pros The first bus cycle sets up the Bank Erase gramming has started. command. During Double Word Program operations the bank s The second latches the bank address in the being programmed will only accept the Read Stainternal state machine and starts the Program/ tus Register command, all other commands will be Erase Controller. ignored. Dual operations are not supported during If the second bus cycle is not Write Bank Erase Double Word Program operations. It is not recomConfirm (D0h), Status Register bits SR4 and SR5 mended to suspend the Double Word Program are set and the command aborts. Erase aborts if command. Typical Program times are given in TaReset turns to VIL. As data integrity cannot be ble 14, Program, Erase Times and Program/Erase guaranteed when the Erase operation is aborted, Endurance Cycles. the bank must be erased again. Programming aborts if Reset goes to VIL. As data Once the command is issued the device outputs integrity cannot be guaranteed when the program the Status Register data when any address within operation is aborted, the memory locations must the bank is read. At the end of the operation the be reprogrammed. bank will remain in Read Status Register mode unSee Appendix C, Figure 21, Double Word Protil a Read Array, Read CFI Query or Read Elecgram Flowchart and Pseudo Code, for the flowtronic Signature command is issued. chart for using the Double Word Program During Bank Erase operations the bank being command. erased will only accept the Read Status Register Quadruple Word Program Command command, all other commands will be ignored. A The Quadruple Word Program command imBank Erase operation cannot be suspended. proves the programming throughput by writing a For optimum performance, Bank Erase compage of four adjacent words in parallel. The four mands should be limited to a maximum of 100 Prowords must differ only for the addresses A0 and gram/Erase cycles per Block. After 100 Program/ A1. Erase cycles the internal algorithm will still operate Programming should not be attempted when VPP properly but some degradation in performance is not at VPPH. The command can be executed if may occur. VPP is below VPPH but the result is not guaranteed. Dual operations are not supported during Bank Five bus write cycles are necessary to issue the Erase operations and the command cannot be Quadruple Word Program command. suspended. s The first bus cycle sets up the Double Word Typical Erase times are given in Table 14, ProProgram Command. gram, Erase Times and Program/Erase Endurance Cycles. s The second bus cycle latches the Address and the Data of the first word to be written.
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The third bus cycle latches the Address and the Data of the second word to be written. s The fourth bus cycle latches the Address and the Data of the third word to be written. s The fifth bus cycle latches the Address and the Data of the fourth word to be written and starts the Program/Erase Controller. Read operations to the bank being programmed output the Status Register content after the programming has started. Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the memory locations must be reprogrammed.
s
During Quadruple Word Program operations the bank being programmed will only accept the Read Status Register command, all other commands will be ignored. Dual operations are not supported during Quadruple Word Program operations. It is not recommended to suspend the Quadruple Word Program command. Typical Program times are given in Table 14, Program, Erase Times and Program/Erase Endurance Cycles. See Appendix C, Figure 22, Quadruple Word Program Flowchart and Pseudo Code, for the flowchart for using the Quadruple Word Program command.
Table 7. Factory Program Commands
Command Phase Cycles Bus Write Operations 1st Add
BKA
2nd Data
80h
3rd Data
D0h
4th Data Add Data Add
5th Data
Add
BKA
Add
Bank Erase Double Word Program(2) Quadruple Word Program(3)
2
3 5
BKA BKA
30h 55h
WA1 WA1
PD1 PD1
WA2 WA2
PD2 PD2 WA3 PD3 WA4 PD4
Note: 1. WA=Word Address in targeted bank, BKA= Bank Address, PD=Program Data, WA1 is the Start Address. 2. Word Addresses 1 and 2 must be consecutive Addresses differing only for A0. 3. Word Addresses 1,2,3 and 4 must be consecutive Addresses differing only for A0 and A1.
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STATUS REGISTER The M58CR064 has two Status Registers, one for each bank. The Status Registers provide information on the current or previous Program or Erase operations executed in each bank. Issue a Read Status Register command to read the contents of the Status Register, refer to Read Status Register Command section for more details. To output the contents, the Status Register is latched and updated on the falling edge of the Chip Enable or Output Enable signals, and can be read until Chip Enable or Output Enable returns to VIH. The Status Register can only be read using single asynchronous or single synchronous reads. Bus Read operations from any address within the bank, always read the Status Register during Program and Erase operations. The various bits convey information about the status and any errors of the operation. Bits SR7, SR6 and SR2 give information on the status of the bank and are set and reset by the device. Bits SR5, SR4, SR3 and SR1 give information on errors, they are set by the device but must be reset by issuing a Clear Status Register command or a hardware reset. If an error bit is set to `1' the Status Register should be reset before issuing another command. The bits in the Status Register are summarized in Table 8, Status Register Bits. Refer to Table 8 in conjunction with the following text descriptions. Program/Erase Controller Status Bit (SR7). The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive in the addressed bank. When the Program/Erase Controller Status bit is Low (set to `0'), the Program/Erase Controller is active; when the bit is High (set to `1'), the Program/Erase Controller is inactive, and the device is ready to process a new command. The Program/Erase Controller Status is Low immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the bit is High. During Program, Erase, operations the Program/ Erase Controller Status bit can be polled to find the end of the operation. Other bits in the Status Register should not be tested until the Program/Erase Controller completes the operation and the bit is High. After the Program/Erase Controller completes its operation the Erase Status, Program Status, VPP Status and Block Lock Status bits should be tested for errors. Erase Suspend Status Bit (SR6). The Erase Suspend Status bit indicates that an Erase operation has been suspended or is going to be sus-
pended in the addressed block. When the Erase Suspend Status bit is High (set to `1'), a Program/ Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The Erase Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). SR7 is set within 30s of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued the Erase Suspend Status bit returns Low. Erase Status Bit (SR5). The Erase Status bit can be used to identify if the memory has failed to verify that the block or bank has erased correctly. When the Erase Status bit is High (set to `1'), the Program/Erase Controller has applied the maximum number of pulses to the block or bank and still failed to verify that it has erased correctly. The Erase Status bit should be read once the Program/ Erase Controller Status bit is High (Program/Erase Controller inactive). Once set High, the Erase Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Program Status Bit (SR4). The Program Status bit is used to identify a Program failure. When the Program Status bit is High (set to `1'), the Program/Erase Controller has applied the maximum number of pulses to the byte and still failed to verify that it has programmed correctly. The Program Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Once set High, the Program Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new command is issued, otherwise the new command will appear to fail. VPP Status Bit (SR3). The V PP Status bit can be used to identify an invalid voltage on the VPP pin during Program and Erase operations. The VPP pin is only sampled at the beginning of a Program or Erase operation. Indeterminate results can occur if V PP becomes invalid during an operation. When the VPP Status bit is Low (set to `0'), the voltage on the V PP pin was sampled at a valid voltage; when the V PP Status bit is High (set to `1'), the VPP pin has a voltage that is below the V PP Lockout Voltage, VPPLK, the memory is protected and Program and Erase operations cannot be performed.
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Once set High, the V PP Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Program Suspend Status Bit (SR2). The Program Suspend Status bit indicates that a Program operation has been suspended in the addressed block. When the Program Suspend Status bit is High (set to `1'), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The Program Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). SR2 is set within 5s of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode. Table 8. Status Register Bits
Bit SR7 Name P/E.C. Status Type Status '0' '1' SR6 Erase Suspend Status Status '0' '1' SR5 Erase Status Error '0' '1' SR4 Program Status Error '0' '1' SR3 VPP Status Error '0' '1' SR2 Program Suspend Status Status '0' '1' SR1 SR0
Note: Logic level '1' is High, '0' is Low.
When a Program/Erase Resume command is issued the Program Suspend Status bit returns Low. Block Protection Status Bit (SR1). The Block Protection Status bit can be used to identify if a Program or Block Erase operation has tried to modify the contents of a locked block. When the Block Protection Status bit is High (set to `1'), a Program or Erase operation has been attempted on a locked block. Once set High, the Block Protection Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new command is issued, otherwise the new command will appear to fail. Reserved Bit (SR0). SR0 is reserved. Its value must be masked.
Logic Level '1' Ready Busy Erase Suspended
Definition
Erase In progress or Completed Erase Error Erase Success Program Error Program Success VPP Invalid, Abort VPP OK Program Suspended Program In Progress or Completed Program/Erase on protected Block, Abort No operation to protected blocks Reserved
Block Protection Status
Error '0'
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CONFIGURATION REGISTER The Configuration Register is used to configure the type of bus access that the memory will perform. Refer to Read Modes section for details on read operations. The Configuration Register is set through the Command Interface. After a Reset or Power-Up the device is configured for asynchronous page read (CR15 = 1). The Configuration Register bits are described in Table 9. They specify the selection of the burst length, burst type, burst X latency and the Read operation. Refer to Figures 6 and 7 for examples of synchronous burst configurations. Read Select Bit (CR15) The Read Select bit, CR15, is used to switch between asynchronous and synchronous Bus Read operations. When the Read Select bit is set to '1', read operations are asynchronous; when the Read Select bit is set to '0', read operations are synchronous. Synchronous Burst Read is supported in both parameter and main blocks and can be performed across banks. On reset or power-up the Read Select bit is set to'1' for asynchronous access. X-Latency Bits (CR13-CR11) The X-Latency bits are used during Synchronous Read operations to set the number of clock cycles between the address being latched and the first data becoming available. For correct operation the X-Latency bits can only assume the values in Table 9, Configuration Register. The correspondence between X-Latency settings and the maximum sustainable frequency must be calculated taking into account some system parameters. Two conditions must be satisfied: 1. Depending on whether tAVK_CPU or t DELAY is supplied either one of the following two equations must be satisfied: (n + 1) t K tACC - tAVK_CPU + tQVK_CPU (n + 2) tK tACC + tDELAY + tQVK_CPU 2. and also tK > tKQV + tQVK_CPU where n is the chosen X-Latency configuration code tK is the clock period tAVK_CPU is clock to address valid, L Low, or E Low, whichever occurs last tDELAY is address valid, L Low, or E Low to clock, whichever occurs last tQVK_CPU is the data setup time required by the system CPU, tKQV is the clock to data valid time tACC is the random access time of the device.
Refer to Figure 6, X-Latency and Data Output Configuration Example. Power-Down Bit (CR10) The Power-Down bit is used to enable or disable the power-down function. When the Power-Down bit is set to `0' the powerdown function is disabled. If the Reset/PowerDown, RP, pin goes Low, VIL, the device is reset and the supply current, IDD, is reduced to the standby value, IDD3. When the Power-Down bit is set to `1' the powerdown function is enabled. If the Reset/PowerDown, RP, pin goes Low, VIL, the device goes into the power-down state and the supply current, IDD, is reduced to the power-down value, IDD2. The recovery time after a Reset/Power-Down, RP, pulse is significantly longer when power-down is enabled (see Table 24). After a reset the Power-Down Bit is set to `0'. Wait Configuration Bit (CR8) In burst mode the Wait bit controls the timing of the Wait output pin, WAIT. When the Wait bit is '0' the Wait output pin is asserted during the wait state. When the Wait bit is '1' (default) the Wait output pin is asserted one clock cycle before the wait state. WAIT is asserted during a continuous burst and also during a 4 or 8 burst length if no-wrap configuration is selected. WAIT is not asserted during asynchronous reads, single synchronous reads or during latency in synchronous reads. Burst Type Bit (CR7) The Burst Type bit is used to configure the sequence of addresses read as sequential or interleaved. When the Burst Type bit is '0' the memory outputs from interleaved addresses; when the Burst Type bit is '1' (default) the memory outputs from sequential addresses. See Tables 10, Burst Type Definition, for the sequence of addresses output from a given starting address in each mode. Valid Clock Edge Bit (CR6) The Valid Clock Edge bit, CR6, is used to configure the active edge of the Clock, K, during Synchronous Burst Read operations. When the Valid Clock Edge bit is '0' the falling edge of the Clock is the active edge; when the Valid Clock Edge bit is '1' the rising edge of the Clock is active. Wrap Burst Bit (CR3) The burst reads can be confined inside the 4 or 8 Word boundary (wrap) or overcome the boundary (no wrap). The Wrap Burst bit is used to select between wrap and no wrap. When the Wrap Burst bit is set to `0' the burst read wraps; when it is set to `1' the burst read does not wrap.
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Burst length Bits (CR2-CR0) The Burst Length bits set the number of Words to be output during a Synchronous Burst Read operation as result of a single address latch cycle. They can be set for 4 words, 8 words or continuous burst, where all the words are read sequentially. In continuous burst mode the burst sequence can cross bank boundaries. In continuous burst mode or in 4, 8 words no-wrap, depending on the starting address, the device asserts the WAIT output to indicate that a delay is necessary before the data is output. Table 9. Configuration Register
Bit CR15 CR14 010 011 100 CR13-CR11 X-Latency 101 111 5 clock latency Reserved Description 0 Read Select 1 Asynchronous Read (Default at power-on) Reserved 2 clock latency 3 clock latency 4 clock latency Value Synchronous Read Description
If the starting address is aligned to a 4 word boundary no wait states are needed and the WAIT output is not asserted. If the starting address is shifted by 1,2 or 3 positions from the four word boundary, WAIT will be asserted for 1, 2 or 3 clock cycles when the burst sequence crosses the first 64 word boundary, to indicate that the device needs an internal delay to read the successive words in the array. WAIT will be asserted only once during a continuous burst access. See also Table 10, Burst Type Definition. CR14, CR9, CR5 and CR4 are reserved for future use.
Other configurations reserved 0 CR10 CR9 0 CR8 Wait Configuration 1 0 CR7 Burst Type 1 0 CR6 CR5-CR4 0 CR3 Wrap Burst 1 001 CR2-CR0 Burst Length 010 111 No Wrap 4 words 8 words Continuous (CR7 must be set to `1') Valid Clock Edge 1 Rising Clock edge Reserved Wrap Sequential (default) Falling Clock edge Power-Down 1 Power-Down disabled Power-Down enabled Reserved
WAIT is active during wait state WAIT is active one data cycle before wait state (default)
Interleaved
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Table 10. Burst Type Definition
Mode Start Address 4 Words Sequential 0 1 2 3 ... Wrap 7 ... 60 61 62 63 Sequential 0 1 2 3 ... No-wrap 7 ... 60 61 62 63 60-61-62-63 61-62-63-WAIT-64 62-63-WAIT-WAIT64-65 63-WAIT-WAITWAIT-64-65-66 60-61-62-63-64-65-6667 61-62-63-WAIT-64-6566-67-68 62-63-WAIT-WAIT-6465-66-67-68-69 63-WAIT-WAIT-WAIT64-65-66-67-68-69-70 7-8-9-10 7-8-9-10-11-12-13-14 Same as for Wrap (Wrap /No Wrap has no effect on Continuous Burst ) 0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6 Interleaved Sequential 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9... 3-4-5-6-7-8-9-10 Interleaved 60-61-62-63-64-65-66... 61-62-63-WAIT-64-65-66... 62-63-WAIT-WAIT-64-65-66... 63-WAIT-WAIT-WAIT-64-6566... 7-4-5-6 7-6-5-4 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 7-8-9-10-11-12-13... 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 Interleaved 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 8 Words Continuous Burst Sequential 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 Interleaved 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 0-1-2-3-4-5-6... 1-2-3-4-5-6-7... 2-3-4-5-6-7-8... 3-4-5-6-7-8-9...
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Figure 6. X-Latency and Data Output Configuration Example
X-latency 1st cycle K 2nd cycle 3rd cycle 4th cycle
E
L
A21-A0 tDELAY
VALID ADDRESS tAVK_CPU tACC tQVK_CPU tKQV tK tQVK_CPU
DQ15-DQ0 VALID DATA VALID DATA
Note. Settings shown: X-latency = 4, Data Output held for one clock cycle
AI90005
Figure 7. Wait Configuration Example
E
K
L
A21-A0
VALID ADDRESS
DQ15-DQ0
VALID DATA VALID DATA
NOT VALID
VALID DATA
WAIT CR8 = '0'
WAIT CR8 = '1'
AI90006b
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
READ MODES Read operations can be performed in two different ways depending on the settings in the Configuration Register. If the clock signal is `don't care' for the data output, the read operation is Asynchronous; if the data output is synchronized with clock, the read operation is Synchronous. The Read mode and data output format are determined by the Configuration Register. (See Configuration Register section for details). All banks supports both asynchronous and synchronous read operations. The Dual Bank architecture allows read operations in one bank, while write operations are being executed in the other (see Tables 11 and 12). Asynchronous Read Mode In Asynchronous Read operations the clock signal is `don't care'. The device outputs the data corresponding to the address latched, that is the memory array, Status Register, Common Flash Interface or Electronic Signature depending on the command issued. CR15 in the Configuration Register must be set to `1' for Asynchronous operations. In Asynchronous Read mode a Page of data is internally read and stored in a Page Buffer. The Page has a size of 4 Words and is addressed by A0 and A1 address inputs. The address inputs A0 and A1 are not gated by Latch Enable in Asynchronous Read mode. The first read operation within the Page has a longer access time (Tacc, Random access time), subsequent reads within the same Page have much shorter access times. If the Page changes then the normal, longer timings apply again. Asynchronous Read operations can be performed in two different ways, Asynchronous Random Access Read and Asynchronous Page Read. Only Asynchronous Page Read takes full advantage of the internal page storage so different timings are applied. See Table 20, Asynchronous Read AC Characteristics, Figure 10, Asynchronous Random Access Read AC Waveform and Figure 11, Asynchronous Page Read AC Waveform for details. Synchronous Burst Read Mode In Synchronous Burst Read mode the data is output in bursts synchronized with the clock. It is possible to perform burst reads across bank boundaries. Synchronous Burst Read mode can only be used to read the memory array. For other read operations, such as Read Status Register, Read CFI and Read Electronic Signature, Single Synchronous Read or Asynchronous Random Access Read must be used.
In Synchronous Burst Read mode the flow of the data output depends on parameters that are configured in the Configuration Register. A burst sequence is started at the first clock edge (rising or falling depending on Valid Clock Edge bit CR6 in the Configuration Register) after the falling edge of Latch Enable or Chip Enable, whichever occurs last. Addresses are internally incremented and after a delay of 2 to 5 clock cycles (X latency bits CR13-CR11) the corresponding data are output on each clock cycle. The number of Words to be output during a Synchronous Burst Read operation can be configured as 4 or 8 Words or Continuous (Burst Length bits CR2-CR0). The data can be configured to remain valid for one or two clock cycles (Data Output Configuration bit CR9). The order of the data output can be modified through the Burst Type and the Wrap Burst bits in the Configuration Register. The burst sequence may be configured to be sequential or interleaved (CR7). The burst reads can be confined inside the 4 or 8 Word boundary (Wrap) or overcome the boundary (No Wrap). If the starting address is aligned to the Burst Length (4 or 8 Words), the wrapped configuration has no impact on the output sequence. Interleaved mode is not allowed in Continuous Burst Read mode or with No Wrap sequences. A WAIT signal may be asserted to indicate to the system that an output delay will occur. This delay will depend on the starting address of the burst sequence; the worst case delay will occur when the sequence is crossing a 64 word boundary and the starting address was at the end of a four word boundary. WAIT is asserted during the Wait state and at the end of 4- and 8-Word Burst. It is deasserted during the X latency and when output data are valid. In Continuous Burst Read mode a Wait state will occur when crossing the first 64 Word boundary. If the burst starting address is aligned to a 4 Word Page, the Wait state will not occur. The WAIT signal is active Low. The WAIT signal is meaningful only in Synchronous Burst Read mode, in other modes, WAIT is not asserted (except for Read Array mode). See Table 21, Synchronous Read AC Characteristics and Figure 12, Synchronous Burst Read AC Waveform for details. Single Synchronous Read Mode Single Synchronous Read operations are similar to Synchronous Burst Read operations except that only the first data output after the X latency is valid. Other Configuration Register parameters have no effect on Single Synchronous Read operations.
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Synchronous Single Reads are used to read the Electronic Signature, Status Register, CFI, Block Protection Status, Configuration Register Status or Protection Register. When the addressed bank is in Read CFI, Read Status Register or Read Electronic Signature mode, the WAIT signal is always deasserted. See Table 21, Synchronous Read AC Characteristics and Figure 13, Single Synchronous Read AC Waveform for details.
DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE The Dual Operations feature simplifies the softthen a Program command can be issued to anothware management of the device and allows code er block, so the device can have one block in to be executed from one bank while the other bank Erase Suspend mode, one programming and the is being programmed or erased. other bank in Read mode. Bus Read operations are allowed in the other bank between setup and The Dual operations feature means that while proconfirm cycles of program or erase operations. gramming or erasing in one bank, Read operaThe combination of these features means that tions are possible in the other bank with zero read operations are possible at any moment. latency (only one bank at a time is allowed to be in Program or Erase mode). If a Read operation is reTables 11 and 12 show the dual operations possiquired in a bank which is programming or erasing, ble in the other bank and in the same bank. For a the Program or Erase operation can be suspendcomplete list of possible commands refer to Aped. Also if the suspended operation was Erase pendix D, Command Interface State Tables. Table 11. Dual Operations Allowed In Other Bank
Commands allowed in other bank Status of bank Read Array Yes Yes Yes Yes Yes Read Status Register Yes Yes Yes Yes Yes Read CFI Query Yes Yes Yes Yes Yes Read Electronic Program Signature Yes Yes Yes Yes Yes Yes - - - Yes Block Erase Yes - - - - Program/ Program/ Erase Erase Suspend Resume Yes - - - - Yes - - Yes Yes
Idle Programming Erasing Program Suspended Erase Suspended
Table 12. Dual Operations Allowed In Same Bank
Commands allowed in same bank Status of bank Read Array Yes - - Yes(1) Yes(1) Read Read Read Status Electronic Program CFI Query Register Signature Yes Yes Yes Yes Yes Yes - - Yes Yes Yes - - Yes Yes Yes - - - Yes(1) Block Erase Yes - - - - Program/ Erase Suspend Yes Yes Yes - - Program/ Erase Resume Yes - - Yes Yes
Idle Programming Erasing Program Suspended Erase Suspended
Note: 1. Not allowed in the Block or Word that is being erased or programmed.
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
BLOCK LOCKING The M58CR064 features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has three levels of protection. s Lock/Unlock - this first level allows softwareonly control of block locking.
s
Lock-Down - this second level requires hardware interaction before locking can be changed. VPP VPPLK - the third level offers a complete hardware protection against program and erase on all blocks (M58CR064C/D only).
s
The first two levels (Lock/Unlock and Lock-Down) are available in M58CR064C/D and M58CR064P/ Q. The third level (VPP VPPLK) is only available for the M58CR064C/D versions, in the M58CR064P/Q this feature has been disabled. For all devices the protection status of each block can be set to Locked, Unlocked, and Lock-Down. Table 13, defines all of the possible protection states (WP, DQ1, DQ0), and Appendix C, Figure 26, shows a flowchart for the locking operations. Reading a Block's Lock Status The lock status of every block can be read in the Read Electronic Signature mode of the device. To enter this mode write 90h to the device. Subsequent reads at the address specified in Table 6, will output the protection status of that block. The lock status is represented by DQ0 and DQ1. DQ0 indicates the Block Lock/Unlock status and is set by the Lock command and cleared by the Unlock command. It is also automatically set when entering Lock-Down. DQ1 indicates the Lock-Down status and is set by the Lock-Down command. It cannot be cleared by software, only by a hardware reset or power-down. The following sections explain the operation of the locking system. Locked State The default status of all blocks on power-up or after a hardware reset is Locked (states (0,0,1) or (1,0,1)). Locked blocks are fully protected from any program or erase. Any program or erase operations attempted on a locked block will return an error in the Status Register. The Status of a Locked block can be changed to Unlocked or Lock-Down using the appropriate software commands. An Unlocked block can be Locked by issuing the Lock command. Unlocked State Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. All unlocked blocks return to the Locked state after a hardware
reset or when the device is powered-down. The status of an unlocked block can be changed to Locked or Locked-Down using the appropriate software commands. A locked block can be unlocked by issuing the Unlock command. Lock-Down State Blocks that are Locked-Down (state (0,1,x))are protected from program and erase operations (as for Locked blocks) but their protection status cannot be changed using software commands alone. A Locked or Unlocked block can be Locked-Down by issuing the Lock-Down command. LockedDown blocks revert to the Locked state when the device is reset or powered-down. The Lock-Down function is dependent on the WP input pin. When WP=0 (VIL), the blocks in the Lock-Down state (0,1,x) are protected from program, erase and protection status changes. When WP=1 (V IH) the Lock-Down function is disabled (1,1,x) and Locked-Down blocks can be individually unlocked to the (1,1,0) state by issuing the software command, where they can be erased and programmed. These blocks can then be re-locked (1,1,1) and unlocked (1,1,0) as desired while WP remains high. When WP is low , blocks that were previously Locked-Down return to the Lock-Down state (0,1,x) regardless of any changes made while WP was high. Device reset or power-down resets all blocks , including those in Lock-Down, to the Locked state. Locking Operations During Erase Suspend Changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. This is useful in the case when another block needs to be updated while an erase operation is in progress. To change block locking during an erase operation, first write the Erase Suspend command, then check the status register until it indicates that the erase operation has been suspended. Next write the desired Lock command sequence to a block and the lock status will be changed. After completing any desired lock, read, or program operations, resume the erase operation with the Erase Resume command. If a block is locked or locked-down during an erase suspend of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete. Locking operations cannot be performed during a program suspend. Refer to Appendix D, Command Interface State Table, for detailed information on which commands are valid during erase suspend.
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Table 13. Lock Status
Current Protection Status(1) (WP, DQ1, DQ0) Current State 1,0,0 1,0,1(2) 1,1,0 1,1,1 0,0,0 0,0,1(2) 0,1,1 Program/Erase Allowed yes no yes no yes no no After Block Lock Command 1,0,1 1,0,1 1,1,1 1,1,1 0,0,1 0,0,1 0,1,1 Next Protection Status(1) (WP, DQ1, DQ0) After Block Unlock Command 1,0,0 1,0,0 1,1,0 1,1,0 0,0,0 0,0,0 0,1,1 After Block Lock-Down Command 1,1,1 1,1,1 1,1,1 1,1,1 0,1,1 0,1,1 0,1,1 After WP transition 0,0,0 0,0,1 0,1,1 0,1,1 1,0,0 1,0,1 1,1,1 or 1,1,0 (3)
Note: 1. The lock status is defined by the write protect pin and by DQ1 (`1' for a locked-down block) and DQ0 (`1' for a locked block) as read in the Read Electronic Signature command with A1 = VIH and A0 = VIL. 2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status. 3. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES The Program and Erase times and the number of Program/ Erase cycles depends on the voltage Program/ Erase cycles per block are shown in Tasupply used. ble 14. In the M58CR064 the maximum number of Table 14. Program, Erase Times and Program, Erase Endurance Cycles
Parameter Condition Min Typ Typical after 100k W/E Cycles 1 3 Max Unit
Parameter Block (4 KWord) Erase(2) Preprogrammed Main Block (32 KWord) Erase Not Preprogrammed Preprogrammed Bank A (16Mbit) Erase Not Preprogrammed Preprogrammed VPP = VDD Bank B (48Mbit) Erase Not Preprogrammed Parameter Block (4 KWord) Program(3) Main Block (32 KWord) Program(3) Word Program (3) Program Suspend Latency Erase Suspend Latency Main Blocks Program/Erase Cycles (per Block) Parameter Blocks Parameter Block (4 KWord) Erase Main Block (32 KWord) Erase Bank A (16Mbit) Erase Bank B (48Mbit) Erase 4Mbit Program VPP = VPPH Quadruple Word 100,000 100,000
0.3 0.8 1.1 11 18 33 54 40 300 10 5 5
2.5 4 4
s s s s s s s ms ms
10
100 10 20
s s s cycles cycles
0.3 0.9 13 39 510 8 8 32 64 256
2.5 4
s s s s ms
Word/ Double Word/ Quadruple Word Program(3) Parameter Block (4 KWord) Program(3) Quadruple Word Word Quadruple Word Word Main Blocks Program/Erase Cycles (per Block) Parameter Blocks
100
s ms ms ms ms
Main Block (32 KWord) Program(3)
1000 2500
cycles cycles
Note: 1. TA = -40 to 85C; VDD = 1.65V to 2V; VDDQ = 1.65V to 3.3V. 2. The difference between Preprogrammed and not preprogrammed is not significant (30ms). 3. Excludes the time needed to execute the command sequence.
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not imTable 15. Absolute Maximum Ratings
Value Symbol TA TBIAS TSTG VIO VDD VDDQ VPP IO tVPPH Parameter Ambient Operating Temperature Temperature Under Bias Storage Temperature Input or Output Voltage Supply Voltage Input/Output Supply Voltage Program Voltage Output Short Circuit Current Time for VPP at VPPH Min -40 -40 -55 -0.5 -0.5 -0.5 -0.5 Max 85 125 155 VDDQ+0.5 2.7 3.6 13 100 100 Unit C C C V V V V mA hours
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
DC AND AC PARAMETERS This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement
Conditions summarized in Table 16, Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters.
Table 16. Operating and AC Measurement Conditions
M58CR064C, M58CR064D, M58CR064P, M58CR064Q 85 Parameter Min VDD Supply Voltage VDDQ Supply Voltage VPP Supply Voltage (Factory environment) VPP Supply Voltage (Application environment) Ambient Operating Temperature Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 1.8 1.8 11.4 -0.4 -40 30 4 0 to VDDQ VDDQ/2 Max 2.0 3.3 12.6 VDDQ +0.4 85 Min 1.7 1.7 11.4 -0.4 -40 30 4 0 to VDDQ VDDQ/2 Max 2.0 3.3 12.6 VDDQ +0.4 85 Min 1.65 1.65 11.4 -0.4 -40 30 4 0 to VDDQ VDDQ/2 Max 2.0 3.3 12.6 VDDQ +0.4 85 Min 1.65 1.65 11.4 -0.4 -40 30 4 0 to VDDQ VDDQ/2 Max 2.0 3.3 12.6 VDDQ +0.4 85 V V V V C pF ns V V 90 100 120 Unit
Figure 8. AC Measurement I/O Waveform
Figure 9. AC Measurement Load Circuit
VDDQ
VDDQ VDDQ/2 0V VDDQ VDD 16.7k
AI06161
DEVICE UNDER TEST 0.1F 0.1F CL 16.7k
CL includes JIG capacitance
AI06162
Table 17. Capacitance
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min 6 8 Max 8 12 Unit pF pF
Note: Sampled only, not 100% tested.
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Table 18. DC Characteristics - Currents
Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Supply Current Asynchronous Read (f=6MHz) Supply Current Synchronous Read (f=40MHz) Test Condition 0V VIN VDDQ 0V VOUT VDDQ E = VIL, G = VIH 4 Word 8 Word Continuous 4 Word Supply Current Synchronous Read (f=54MHz) Supply Current (Power-Down) Supply Current (Standby) Supply Current (Program) IDD4 (1) Supply Current (Erase) VPP = VDD Program/Erase in one Bank, Asynchronous Read in another Bank Program/Erase in one Bank, Synchronous Read in another Bank E = VDD 0.2V VPP = VPPH VPP Supply Current (Program) IPP1(1) VPP Supply Current (Erase) VPP = VDD VPP = VPPH VPP = VDD VPP = VPPH VPP VDD VPP VDD 10 13 20 26 mA mA VPP = VDD VPP = VPPH 10 8 20 15 mA mA 8 Word Continuous IDD2 IDD3 RP = VSS 0.2V E = VDD 0.2V VPP = VPPH IDD1 3 6 8 6 7 10 13 2 10 8 Min Typ Max 1 1 6 13 14 10 16 18 25 10 50 15 Unit A A mA mA mA mA mA mA mA A A mA
Supply Current IDD5 (1,2) (Dual Operations)
16
30
mA
IDD6(1)
Supply Current Program/ Erase Suspended (Standby)
10 2 0.2 2 0.2 100 0.2 0.2
50 5 5 5 5 400 5 5
A mA A mA A A A A
IPP2 IPP3(1)
VPP Supply Current (Read) VPP Supply Current (Standby)
Note: 1. Sampled only, not 100% tested. 2. VDD Dual Operation current is the sum of read and program or erase currents.
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Table 19. DC Characteristics - Voltages
Symbol VIL VIH VOL VOH VPP1 VPPH VPPLK VLKO VRPH Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VPP Program Voltage-Logic VPP Program Voltage Factory Program or Erase Lockout VDD Lock Voltage RP pin Extended High Voltage 1 3.3 IOL = 100A IOH = -100A Program, Erase Program, Erase VDDQ -0.1 1 11.4 1.8 12 1.95 12.6 0.9 Test Condition Min -0.5 VDDQ -0.4 Typ Max 0.4 VDDQ + 0.4 0.1 Unit V V V V V V V V V
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A0-A21 VALID VALID tAVAV tAVLH tLHAX tAXQX
L tLLLH tLLQV tELLH tELQV tLHGL
E tEHQZ tELQX tEHQX
G tGLQV tGLQX tGLTV tELTV tEHTZ tGHQX tGHQZ
Figure 10. Asynchronous Random Access Read AC Waveforms
WAIT tAVQV
Hi-Z
DQ0-DQ15
Hi-Z
VALID
Valid Address Latch
Outputs Enabled
Data Valid
Standby
Note. Write Enable, W, is High.
AI90009b
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
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VALID ADDRESS tAVAV VALID ADDRESS VALID ADDRESS tLHAX VALID ADDRESS tLLQV tLHGL tELQV tELQX tGLTV tELTV tGLQV tGLQX VALID DATA Outputs Enabled Valid Data Standby tAVQV1 VALID DATA VALID DATA VALID DATA
AI90048c
A2-A21
A0-A1
VALID ADDRESS
tAVLH
L
tLLLH
tELLH
Figure 11. Asynchronous Page Read AC Waveforms
E
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
G
Hi-Z
WAIT
DQ0-DQ15
Valid Address Latch
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Table 20. Asynchronous Read AC Characteristics
Symbol tAVAV tAVQV tAVQV1 tAXQX (1) tELTV tELQV (2) Read Timings tELQX (1) tEHTZ tEHQX (1) tEHQZ (1) tGLQV (2) tGLQX (1) tGLTV tGHQX (1) tGHQZ (1) tAVLH Latch Timings tELLH tLHAX tLLLH tLLQV tLHGL tOH tDF tAVADVH tELADVH tADVHAX tADVLADVH tADVLQV tADVHGL tOH tHZ tOE tOLZ tCE tLZ Alt tRC tACC tPAGE tOH Parameter Address Valid to Next Address Valid Address Valid to Output Valid (Random) Address Valid to Output Valid (Page) Address Transition to Output Transition Chip Enable Low to Wait Valid Chip Enable Low to Output Valid Chip Enable Low to Output Transition Chip Enable High to Wait Hi-Z Chip Enable High to Output Transition Chip Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition Output Enable Low to Wait Valid Output Enable High to Output Transition Output Enable High to Output Hi-Z Address Valid to Latch Enable High Chip Enable Low to Latch Enable High Latch Enable High to Address Transition Latch Enable Pulse Width Latch Enable Low to Output Valid (Random) Latch Enable High to Output Enable Low Min Max Max Min Max Max Min Max Min Max Max Min Max Min Max Min Min Min Min Max Min M58CR064 85 85 85 30 0 14 85 0 20 0 20 25 0 14 0 20 10 10 10 10 85 10 90 90 90 30 0 14 90 0 20 0 20 25 0 14 0 20 10 10 10 10 90 10 100 100 100 45 0 14 100 0 20 0 20 25 0 14 0 20 10 10 10 10 100 10 120 120 120 45 0 18 120 0 20 0 20 25 0 18 0 20 10 10 10 10 120 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: 1. Sampled only, not 100% tested. 2. G may be delayed by up to t ELQV - tGLQV after the falling edge of E without increasing tELQV .
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VALID VALID tKHQX tKHQV tKHQX VALID VALID tKHQV NOT VALID tKHQV tKHKL Note 1 tKHKH tEHEL tKHQX tKLKH tEHQX tEHQZ tGHQX tGLQX tGHQZ tGLTV tKHTX tKHTX tKHTV tEHTZ Note 2 Note 2 Valid Valid Data Flow Boundary Crossing Data X Latency Standby
AI90010b
DQ0-DQ15
Hi-Z
A0-A21
VALID ADDRESS
tAVLH
tLLLH
L
tLLKH
tAVKH
K
Figure 12. Synchronous Burst Read AC Waveforms
tELKH
tKHAX
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
E
G
tELTV
Hi-Z
WAIT
Address Latch
Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register. 2. The WAIT signal can be configured to be active during wait state or one cycle before. 3. Address latched and data output on the rising clock edge.
DQ0-DQ15
VALID NOT VALID NOT VALID NOT VALID NOT VALID NOT VALID
Hi-Z
A0-A21
VALID ADDRESS
tAVLH
tLLLH
L tEHQX tKHQV Note 1 tEHEL tKHKH tKHKL tKLKH tEHQZ
tLLKH
tAVKH
K(4)
tELKH
tKHAX
Figure 13. Single Synchronous Read AC Waveforms
E tGLQX tGLQV tGHQX tGHQZ
G tGLTV tEHTZ Note 3
tELTV
Hi-Z
WAIT(2)
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register. 2. The WAIT signal is configured to be active during wait state. 3. WAIT is always deasserted when addressed bank is in Read CFI, Read SR or Read electronic signature mode. WAIT signals valid data if the addressed bank is in Read Array mode. 4. Address latched and data output on the rising clock edge.
AI06232
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Table 21. Synchronous Read AC Characteristics
M58CR064 Symbol Alt Parameter 85 tAVKH tELKH Synchronous Read Timings tELTV tEHEL tEHTZ tKHAX tKHQV tKHTV tKHQX tKHTX tLLKH Clock Specifications tKHKH tKHKL tKLKH tCLKHAX tCLKHQV tAVCLKH tELCLKH Address Valid to Clock High Chip Enable Low to Clock High Chip Enable Low to Wait Valid Chip Enable Pulse Width (subsequent synchronous reads) Chip Enable High to Wait Hi-Z Clock High to Address Transition Clock High to Output Valid Clock High to WAIT Valid Clock High to Output Transition Clock High to WAIT Transition Latch Enable Low to Clock High Clock Period (f=40MHz) tCLK Clock Period (f=54MHz) tCLKHCLKL tCLKLCLKH Clock High to Clock Low Clock Low to Clock High Min Min Max 18 5 5 18 5 5 18 5 5 5 5 ns ns ns Min Min Max Min Max Min Max 7 7 14 20 20 10 14 90 7 7 14 20 20 10 14 100 7 7 14 20 20 10 14 120 7 7 18 20 20 10 18 ns ns ns ns ns ns ns Unit
tCLKHQX tADVLCLKH
Min Min Min
4 7
4 7
4 7
4 7 25
ns ns ns
Note: 1. Sampled only, not 100% tested. 2. For other timings please refer to Table 20, Asynchronous Read AC Characteristics.
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PROGRAM OR ERASE tAVAV VALID ADDRESS tAVWH tWHAX tWHAV VALID ADDRESS
A0-A21 tLHAX
BANK ADDRESS
tAVLH
tLLLH
L tWHLL
tELLH
E tWHEH
tELWL
G tWHWL tWHGL
tGHWL
W tWLWH tWHDX CMD or DATA tWHWPL tWPHWH tQVWPL tWHEL tWHQV STATUS REGISTER tELQV
tDVWH
Figure 14. Write AC Waveforms, Write Enable Controlled
DQ0-DQ15
COMMAND
WP tWHVPL tVPHWH tQVVPL
VPP tWHKV
K CONFIRM COMMAND OR DATA INPUT STATUS REGISTER READ 1st POLLING
AI90011b
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
SET-UP COMMAND
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Table 22. Write AC Characteristics, Write Enable Controlled
M58CR064 Symbol tAVAV tAVLH tAVWH tDVWH tELLH tELWL tELQV Write Enable Controlled Timings tGHWL tLHAX tLLLH tWHAV tWHAX tWHDX tWHEH tWHEL(2) tWHGL tWHLL tWHKV tWHWL tWHQV tWLWH tQVVPL Protection Timings tQVWPL tVPHWH tWHVPL tWHWPL tWPHWH tVPS tWP tAH tDH tCH tCS tWC tDS Alt tWC Parameter 85 Address Valid to Next Address Valid Address Valid to Latch Enable High Address Valid to Write Enable High Input Valid to Write Enable High Chip Enable Low to Latch Enable High Chip Enable Low to Write Enable Low Chip Enable Low to Output Valid Output Enable High to Write Enable Low Latch Enable High to Address Transition Latch Enable Pulse Width Write Enable High to Address Valid Write Enable High to Address Transition Write Enable High to Input Transition Write Enable High to Chip Enable High Write Enable High to Chip Enable Low Write Enable High to Output Enable Low Write Enable High to Latch Enable Low Write Enable High to Clock Valid tWPH Write Enable High to Write Enable Low Write Enable High to Output Valid Write Enable Low to Write Enable High Output (Status Register) Valid to VPP Low Output (Status Register) Valid to Write Protect Low VPP High to Write Enable High Write Enable High to VPP Low Write Enable High to Write Protect Low Write Protect High to Write Enable High Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min 85 10 60 40 10 0 85 20 10 10 0 0 0 0 50 0 0 25 30 105 50 0 0 200 200 200 200 90 90 10 60 40 10 0 90 20 10 10 0 0 0 0 50 0 0 25 30 110 50 0 0 200 200 200 200 100 100 10 60 40 10 0 100 20 10 10 0 0 0 0 50 0 0 25 30 120 50 0 0 200 200 200 200 120 120 10 60 40 10 0 120 20 10 10 0 0 0 0 50 0 0 25 30 140 50 0 0 200 200 200 200 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. Sampled only, not 100% tested. 2. tWHEL has the values shown when reading in the targeted bank. System designers should take this into account and may insert a software No-Op instruction to delay the first read in the same bank after issuing a command. If the read operation is in a different bank tWHEL is 0ns.
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PROGRAM OR ERASE tAVAV VALID ADDRESS tAVEH tEHAX VALID ADDRESS
A0-A21 tLHAX
BANK ADDRESS
tAVLH
tLLLH
L tEHWH
tELLH
W
tWLEL
G tEHEL tEHGL
tGHEL
E tELEH tWHEL tEHDX CMD or DATA tEHWPL tWPHEH tQVWPL STATUS REGISTER tELQV
tDVEH
Figure 15. Write AC Waveforms, Chip Enable Controlled
DQ0-DQ15
COMMAND
WP tEHVPL tVPHEH tQVVPL
VPP tWHKV
K CONFIRM COMMAND OR DATA INPUT STATUS REGISTER READ 1st POLLING
AI90012b
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
SET-UP COMMAND
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Table 23. Write AC Characteristics, Chip Enable Controlled
M58CR064 Symbol tAVAV tAVEH tAVLH tDVEH tEHAX Chip Enable Controlled Timings tEHDX tEHEL tEHGL tEHWH tELEH tELLH tELQV tGHEL tLHAX tLLLH tWHEL(2) tWHKV tWLEL tEHVPL Protection Timings tEHWPL tQVVPL tQVWPL tVPHEH tWPHEH tCS tCH tDS tAH tDH Alt tWC tWC Parameter 85 Address Valid to Next Address Valid Address Valid to Chip Enable High Address Valid to Latch Enable High Input Valid to Write Enable High Chip Enable High to Address Transition Chip Enable High to Input Transition Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min 85 60 10 40 0 0 30 0 0 60 10 85 20 10 10 50 25 0 200 200 0 0 200 200 90 90 60 10 40 0 0 30 0 0 60 10 90 20 10 10 50 25 0 200 200 0 0 200 200 100 100 60 10 40 0 0 30 0 0 60 10 100 20 10 10 50 25 0 200 200 0 0 200 200 120 120 60 10 40 0 0 30 0 0 60 10 120 20 10 10 50 25 0 200 200 0 0 200 200 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
tWPH Chip Enable High to Chip Enable Low Chip Enable High to Output Enable Low Chip Enable High to Write Enable High
tWP Chip Enable Low to Chip Enable High Chip Enable Low to Latch Enable High Latch Enable Low to Output Valid Output Enable High to Chip Enable Low Latch Enable High to Address Transition Latch Enable Pulse Width Write Enable High to Chip Enable Low Write Enable High to Clock Valid Write Enable Low to Chip Enable Low Chip Enable High to VPP Low Chip Enable High to Write Protect Low Output (Status Register) Valid to VPP Low Output (Status Register) Valid to Write Protect Low tVPS VPP High to Chip Enable High Write Protect High to Chip Enable High
Note: 1. Sampled only, not 100% tested. 2. tWHEL has the values shown when reading in the targeted bank. System designers should take this into account and may insert a software No-Op instruction to delay the first read in the same bank after issuing a command. If the read operation is in a different bank tWHEL is 0ns.
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Figure 16. Reset and Power-up AC Waveforms
W, E, G, L
tPLWL tPLEL tPLGL tPLLL
RP tVDHPH VDD, VDDQ Power-Up Reset
AI90013c
tPLPH
Table 24. Reset and Power-up AC Characteristics
Symbol tPLWL tPLEL tPLGL tPLLL tPLPH (1,2) tVDHPH (3) Parameter Reset Low to Write Enable Low, Chip Enable Low, Output Enable Low, Latch Enable Low RP Pulse Width Supply Voltages High to Reset High Test Condition During Program During Erase Other Conditions Min Min Min Min Min 85 10 20 80 50 50 90 10 20 80 50 50 100 10 20 80 50 50 120 10 20 80 50 50 Unit s s ns ns s
Note: 1. The device Reset is possible but not guaranteed if tPLPH < 50ns. 2. Sampled only, not 100% tested. 3. It is important to assert RP in order to allow proper CPU initialization during Power-Up or Reset.
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
PACKAGE MECHANICAL Figure 17. TFBGA56 6.5x10mm - 8x7 ball array, 0.75 mm pitch, Bottom View Package Outline
D D1 FD SD
FE
E
E1
e BALL "A1" ddd e A A1 b A2
BGA-Z20
Note: Drawing is not to scale.
Table 25. TFBGA56 6.5x10mm - 8x7 ball array, 0.75 mm pitch, Package Mechanical Data
millimeters Symbol Typ A A1 A2 b D D1 ddd E E1 e FD FE SD 10.000 4.500 0.750 0.625 2.750 0.375 9.900 - - - - - 0.790 0.400 6.500 5.250 0.350 6.400 - 0.450 6.600 - 0.100 10.100 - - - - - 0.3937 0.1772 0.0295 0.0246 0.1083 0.0148 0.3898 - - - - - Min 1.010 0.250 Max 1.200 0.400 0.0311 0.0157 0.2559 0.2067 0.0138 0.2520 - 0.0177 0.2598 - 0.0039 0.3976 - - - - - Typ Min 0.0398 0.0098 Max 0.0472 0.0157 inches
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Figure 18. TFBGA56 Daisy Chain - Package Connections (Top view through package)
1 2 3 4 5 6 7 8
A
B
C
D
E
F
G
AI07731
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Figure 19. TFBGA56 Daisy Chain - PCB Connection Proposal (Top view through package)
1 START POINT A 2 3 4 5 6 7 8
B
C
D
E
F
G
END POINT
AI07755
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
PART NUMBERING Table 26. Ordering Information Scheme
Example: Device Type M58 Architecture C = Dual Bank, Burst Mode Operating Voltage R = VDD = 1.65V to 2.0V, VDDQ = 1.65V to 3.3V Device Function 064C = 64 Mbit (x16), Dual Bank: 1/4-3/4 partitioning, Top Boot 064D = 64 Mbit (x16), Dual Bank: 1/4-3/4 partitioning, Bottom Boot 064P = 64 Mbit (x16), Dual Bank: 1/4-3/4 partitioning, Top Boot, VPP protection feature disabled 064Q = 64 Mbit (x16), Dual Bank: 1/4-3/4 partitioning, Bottom Boot, VPP protection feature disabled Speed 85 = 85ns 90 = 90ns 10 = 100ns 12 = 120ns Package ZB = TFBGA56: 6.5 x 10mm, 0.75 mm pitch Temperature Range 6 = -40 to 85C Option T = Tape & Reel packing M58CR064C 85 ZB 6 T
Table 27. Daisy Chain Ordering Scheme
Example: Device Type M58CR064 Daisy Chain ZB = TFBGA56: 6.5 x 10mm, 0.75 mm pitch Option T = Tape & Reel Packing M58CR064 -ZB T
Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
APPENDIX A. BLOCK ADDRESS TABLES Table 28. Top Boot Block Addresses, M58CR064C, M58CR064P
Bank # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Bank A 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Size (KWord) 4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range 3FF000-3FFFFF 3FE000-3FEFFF 3FD000-3FDFFF 3FC000-3FCFFF 3FB000-3FBFFF 3FA000-3FAFFF 3F9000-3F9FFF 3F8000-3F8FFF 3F0000-3F7FFF 3E8000-3EFFFF 3E0000-3E7FFF 3D8000-3DFFFF 3D0000-3D7FFF 3C8000-3CFFFF 3C0000-3C7FFF Bank B 3B8000-3BFFFF 3B0000-3B7FFF 3A8000-3AFFFF 3A0000-3A7FFF 398000-39FFFF 390000-397FFF 388000-38FFFF 380000-387FFF 378000-37FFFF 370000-377FFF 368000-36FFFF 360000-367FFF 358000-35FFFF 350000-357FFF 348000-34FFFF 340000-347FFF 338000-33FFFF 330000-337FFF 328000-32FFFF 320000-327FFF 318000-31FFFF 310000-317FFF 308000-30FFFF 300000-307FFF 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 2F8000-2FFFFF 2F0000-2F7FFF 2E8000-2EFFFF 2E0000-2E7FFF 2D8000-2DFFFF 2D0000-2D7FFF 2C8000-2CFFFF 2C0000-2C7FFF 2B8000-2BFFFF 2B0000-2B7FFF 2A8000-2AFFFF 2A0000-2A7FFF 298000-29FFFF 290000-297FFF 288000-28FFFF 280000-287FFF 278000-27FFFF 270000-277FFF 268000-26FFFF 260000-267FFF 258000-25FFFF 250000-257FFF 248000-24FFFF 240000-247FFF 238000-23FFFF 230000-237FFF 228000-22FFFF 220000-227FFF 218000-21FFFF 210000-217FFF 208000-20FFFF 200000-207FFF 1F8000-1FFFFF 1F0000-1F7FFF 1E8000-1EFFFF 1E0000-1E7FFF 1D8000-1DFFFF 1D0000-1D7FFF 1C8000-1CFFFF 1C0000-1C7FFF
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
79 80 81 82 83 84 85 86 87 88 89 90 91 92 Bank B 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 1B8000-1BFFFF 1B0000-1B7FFF 1A8000-1AFFFF 1A0000-1A7FFF 198000-19FFFF 190000-197FFF 188000-18FFFF 180000-187FFF 178000-17FFFF 170000-177FFF 168000-16FFFF 158000-15FFFF 150000-157FFF 148000-14FFFF 140000-147FFF 138000-13FFFF 130000-137FFF 128000-12FFFF 120000-127FFF 118000-11FFFF 110000-117FFF 108000-10FFFF 100000-107FFF 0F8000-0FFFFF 0F0000-0F7FFF 0E8000-0EFFFF 0E0000-0E7FFF 0D8000-0DFFFF 0D0000-0D7FFF 0C8000-0CFFFF Bank B 160000-167FFF 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 0C0000-0C7FFF 0B8000-0BFFFF 0B0000-0B7FFF 0A8000-0AFFFF 0A0000-0A7FFF 098000-09FFFF 090000-097FFF 088000-08FFFF 080000-087FFF 078000-07FFFF 070000-077FFF 068000-06FFFF 060000-067FFF 058000-05FFFF 050000-057FFF 048000-04FFFF 040000-047FFF 038000-03FFFF 030000-037FFF 028000-02FFFF 020000-027FFF 018000-01FFFF 010000-017FFF 008000-00FFFF 000000-007FFF
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Table 29. Bottom Boot Block Addresses, M58CR064D, M58CR064Q
Bank # 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 Bank B 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 Size (KWord) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range 3F8000-3FFFFF 3F0000-3F7FFF 3E8000-3EFFFF 3E0000-3E7FFF 3D8000-3DFFFF 3D0000-3D7FFF 3C8000-3CFFFF 3C0000-3C7FFF 3B8000-3BFFFF 3B0000-3B7FFF 3A8000-3AFFFF 3A0000-3A7FFF 398000-39FFFF 390000-397FFF 388000-38FFFF Bank B 380000-387FFF 378000-37FFFF 370000-377FFF 368000-36FFFF 360000-367FFF 358000-35FFFF 350000-357FFF 348000-34FFFF 340000-347FFF 338000-33FFFF 330000-337FFF 328000-32FFFF 320000-327FFF 318000-31FFFF 310000-317FFF 308000-30FFFF 300000-307FFF 2F8000-2FFFFF 2F0000-2F7FFF 2E8000-2EFFFF 2E0000-2E7FFF 2D8000-2DFFFF 2D0000-2D7FFF 2C8000-2CFFFF 2C0000-2C7FFF 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 2B8000-2BFFFF 2B0000-2B7FFF 2A8000-2AFFFF 2A0000-2A7FFF 298000-29FFFF 290000-297FFF 288000-28FFFF 280000-287FFF 278000-27FFFF 270000-277FFF 268000-26FFFF 260000-267FFF 258000-25FFFF 250000-257FFF 248000-24FFFF 240000-247FFF 238000-23FFFF 230000-237FFF 228000-22FFFF 220000-227FFF 218000-21FFFF 210000-217FFF 208000-20FFFF 200000-207FFF 1F8000-1FFFFF 1F0000-1F7FFF 1E8000-1EFFFF 1E0000-1E7FFF 1D8000-1DFFFF 1D0000-1D7FFF 1C8000-1CFFFF 1C0000-1C7FFF 1B8000-1BFFFF 1B0000-1B7FFF 1A8000-1AFFFF 1A0000-1A7FFF 198000-19FFFF 190000-197FFF 188000-18FFFF 180000-187FFF
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
54 53 52 51 50 49 48 Bank B 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Bank A 31 30 29 28 27 26 25 24 23 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 178000-17FFFF 170000-177FFF 168000-16FFFF 160000-167FFF 158000-15FFFF 150000-157FFF 148000-14FFFF 140000-147FFF 138000-13FFFF 130000-137FFF 120000-127FFF 118000-11FFFF 110000-117FFF 108000-10FFFF 100000-107FFF 0F8000-0FFFFF 0F0000-0F7FFF 0E8000-0EFFFF 0E0000-0E7FFF 0D8000-0DFFFF 0D0000-0D7FFF 0C8000-0CFFFF 0C0000-0C7FFF 0B8000-0BFFFF 0B0000-0B7FFF 0A8000-0AFFFF 0A0000-0A7FFF 098000-09FFFF 090000-097FFF 088000-08FFFF 080000-087FFF Bank A 128000-12FFFF 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4 078000-07FFFF 070000-077FFF 068000-06FFFF 060000-067FFF 058000-05FFFF 050000-057FFF 048000-04FFFF 040000-047FFF 038000-03FFFF 030000-037FFF 028000-02FFFF 020000-027FFF 018000-01FFFF 010000-017FFF 008000-00FFFF 007000-007FFF 006000-006FFF 005000-005FFF 004000-004FFF 003000-003FFF 002000-002FFF 001000-001FFF 000000-000FFF
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
APPENDIX B. COMMON FLASH INTERFACE The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the Read CFI Query Command is issued the device enters CFI Query mode and the data structure is read from the memory. Tables 30, 31, Table 30. Query Structure Overview
Offset 00h 10h 1Bh 27h P A Reserved CFI Query Identification String System Interface Information Device Geometry Definition Primary Algorithm-specific Extended Query table Alternate Algorithm-specific Extended Query table Sub-section Name Description Reserved for algorithm-specific information Command set ID and algorithm data offset Device timing & voltage information Flash device layout Additional information specific to the Primary Algorithm (optional) Additional information specific to the Alternate Algorithm (optional) Lock Protection Register Unique device Number and User Programmable OTP
32, 33, 34 and 35 show the addresses used to retrieve the data. The Query data is always presented on the lowest order data outputs (DQ0-DQ7), the other outputs (DQ8-DQ15) are set to 0. The CFI data structure also contains a security area where a 64 bit unique security number is written (see Figure 5, Security Block and Protection Register Memory Map). This area can be accessed only in Read mode by the final user. It is impossible to change the security number after it has been written by ST. Issue a Read Array command to return to Read mode.
80h
Security Code Area
Note: The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections detailed in Tables 31, 32, 33, 34 and 35. Query data is always presented on the lowest order data outputs.
Table 31. CFI Query Identification String
Offset 00h 01h 02h 03h 04h-0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Sub-section Name 0020h 88CAh 88CBh 8801h 8802h reserved reserved reserved 0051h 0052h 0059h 0003h 0000h offset = P = 0039h 0000h 0000h 0000h value = A = 0000h 0000h Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm Address for Primary Algorithm extended Query table (see Table 33) Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported Address for Alternate Algorithm extended Query table p = 39h NA NA Query Unique ASCII String "QRY" Manufacturer Code Device Code (M58CR064C/D/P/Q) Reserved Reserved Reserved "Q" "R" "Y" Description Value ST Top Bottom
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Table 32. CFI Query System Interface Information
Offset 1Bh Data 0017h Description VDD Logic Supply Minimum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts VDD Logic Supply Maximum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts VPP [Programming] Supply Minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts VPP [Programming] Supply Maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts Typical time-out per single byte/word program = 2n s Typical time-out for quadruple word program = 2n s Typical time-out per individual block erase = 2n ms Typical time-out for full chip erase = 2n ms Maximum time-out for word program = 2n times typical Maximum time-out for quadruple word = 2n times typical Maximum time-out per individual block erase = 2n times typical Maximum time-out for chip erase = 2n times typical Value 1.7V
1Ch
0020h
2.0V
1Dh
0017h
1.7V
1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h
00C0h 0004h 0003h 000Ah 0000h 0003h 0004h 0002h 0000h
12V 16s 8s 1s NA 128s 128s 4s NA
Table 33. Device Geometry Definition
Offset Word Mode 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh M58CR064C/P 2Fh 30h 31h 32h 33h 34h 35h 38h Data 0017h 0001h 0000h 0003h 0000h 0002h 007Eh 0000h 0000h 0001h 0007h 0000h 0020h 0000h 0000h Description Device Size = 2n in number of bytes Flash Device Interface Code description Maximum number of bytes in multi-byte program or page = 2n Number of identical sized erase block regions within the device bit 7 to 0 = x = number of Erase Block Regions Region 1 Information Number of identical-size erase blocks = 007Eh+1 Region 1 Information Block size in Region 1 = 0100h * 256 byte Region 2 Information Number of identical-size erase blocks = 000Eh+1 Region 2 Information Block size in Region 2 = 0020h * 256 byte Reserved for future erase block region information Value 8 MByte x16 Async. 8 Byte 2 127 64 KByte 8 8 KByte NA
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Offset Word Mode 2Dh 2Eh M58CR064D/Q 2Fh 30h 31h 32h 33h 34h 35h 38h
Data 0007h 0000h 0020h 0000h 007Eh 0000h 0000h 0001h 0000h
Description Region 1 Information Number of identical-size erase block = 0007h+1 Region 1 Information Block size in Region 1 = 0020h * 256 byte Region 2 Information Number of identical-size erase block = 007Eh+1 Region 2 Information Block size in Region 2 = 0100h * 256 byte Reserved for future erase block region information
Value 8 8 KByte 127 64 KByte NA
Table 34. Primary Algorithm-Specific Extended Query Table
Offset (P)h = 39h Data 0050h 0052h 0049h (P+3)h = 3Ch (P+4)h = 3Dh (P+5)h = 3Eh 0031h 0030h 00E6h 0003h (P+7)h = 40h (P+8)h = 41h 0000h 0000h Major version number, ASCII Minor version number, ASCII Extended Query table contents for Primary Algorithm. Address (P+5)h contains less significant byte. bit bit bit bit bit bit bit bit bit bit bit 0 1 2 3 4 5 6 7 8 9 10 to 31 Chip Erase supported (1 = Yes, 0 = No) Erase Suspend supported (1 = Yes, 0 = No) Program Suspend supported (1 = Yes, 0 = No) Legacy Lock/Unlock supported (1 = Yes, 0 = No) Queued Erase supported (1 = Yes, 0 = No) Instant individual block locking supported (1 = Yes, 0 = No) Protection bits supported (1 = Yes, 0 = No) Page mode read supported (1 = Yes, 0 = No) Synchronous read supported (1 = Yes, 0 = No) Simultaneous operation supported (1 = Yes, 0 = No) Reserved; undefined bits are `0'. If bit 31 is '1' then another 31 bit field of optional features follows at the end of the bit-30 field. No Yes Yes No No Yes Yes Yes Yes Yes Primary Algorithm extended Query table unique ASCII string "PRI" Description Value "P" "R" "I" "1" "0"
(P+9)h = 42h
0001h
Supported Functions after Suspend Read Array, Read Status Register and CFI Query bit 0 Program supported after Erase Suspend (1 = Yes, 0 = No) bit 7 to 1 Reserved; undefined bits are `0' Block Protect Status Defines which bits in the Block Status Register section of the Query are implemented. bit 0 Block protect Status Register Lock/Unlock bit active (1 = Yes, 0 = No) bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No) bit 15 to 2 Reserved for future use; undefined bits are `0' VDD Logic Supply Optimum Program/Erase voltage (highest performance) bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100 mV
Yes
(P+A)h = 43h (P+B)h = 44h
0003h 0000h
Yes Yes 1.8V
(P+C)h = 45h
0018h
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Offset (P+D)h = 46h (P+E)h = 47h (P+F)h = 48h (P+10)h = 49h (P+11)h = 4Ah (P+12)h = 4Bh Data 00C0h 0000h Description VPP Supply Optimum Program/Erase voltage bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100 mV Reserved Value 12V
Table 35. Burst Read Information
Offset (P+13)h = 4Ch Data 0003h Description Page-mode read capability bits 0-7 'n' such that 2n HEX value represents the number of readpage bytes. See offset 28h for device word width to determine page-mode data output width. Number of synchronous mode read configuration fields that follow. Synchronous mode read capability configuration 1 bit 3-7 Reserved bit 0-2 'n' such that 2n+1 HEX value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. A value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device's burstable address space. This field's 3-bit value can be written directly to the read configuration register bit 0-2 if the device is configured for its maximum word width. See offset 28h for word width to determine the burst data output width. Synchronous mode read capability configuration 2 Synchronous mode read capability configuration 3 Max operating clock frequency (MHz) Supported handshaking signal (WAIT pin) bit 0 during synchronous read (1 = Yes, 0 = No) bit 1 during asynchronous read (1 = Yes, 0 = No) Value 8 Bytes
(P+14)h = 4Dh (P+15)h = 4Eh
0003h 0001h
3 4
(P+16)h = 4Fh (P+17)h = 50h (P+18)h = 51h (P+19)h = 52h
0002h 0007h 0036h 0001h
8 Cont. 54 MHz Yes No
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APPENDIX C. FLOWCHARTS AND PSEUDO CODES Figure 20. Program Flowchart and Pseudo Code
Start
Write 40h or 10h
program_command (addressToProgram, dataToProgram) {: writeToFlash (bank_address, 0x40) ; /*or writeToFlash (bank_address, 0x10) ; */ writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/
Write Address & Data
Read Status Register
SR7 = 1 YES SR3 = 0 YES SR4 = 0 YES SR1 = 0 YES End
NO } while (status_register.SR7== 0) ;
NO
VPP Invalid Error (1, 2)
if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ;
NO
Program Error (1, 2)
if (status_register.SR4==1) /*program error */ error_handler ( ) ;
NO
Program to Protected Block Error (1, 2)
if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ;
}
AI06170
Note: 1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Figure 21. Double Word Program Flowchart and Pseudo code
Start
Write 30h
Write Address 1 & Data 1 (3)
Write Address 2 & Data 2 (3)
double_word_program_command (addressToProgram1, dataToProgram1, addressToProgram2, dataToProgram2) { writeToFlash (bank_address, 0x30) ; writeToFlash (addressToProgram1, dataToProgram1) ; /*see note (3) */ writeToFlash (addressToProgram2, dataToProgram2) ; /*see note (3) */ /*Memory enters read status state after the Program command*/ do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/
Read Status Register
SR7 = 1 YES SR3 = 0 YES SR4 = 0 YES SR1 = 0 YES End
NO } while (status_register.b7== 0) ;
NO
VPP Invalid Error (1, 2)
if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ;
NO
Program Error (1, 2)
if (status_register.SR4==1) /*program error */ error_handler ( ) ;
NO
Program to Protected Block Error (1, 2)
if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ;
}
AI06171
Note: 1. Status check of b1 (Protected Block), b3 (V PP Invalid) and b4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase operations. 3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0.
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Figure 22. Quadruple Word Program Flowchart and Pseudo Code
Start
Write 55h
Write Address 1 & Data 1 (3)
quadruple_word_program_command (addressToProgram1, dataToProgram1, addressToProgram2, dataToProgram2, addressToProgram3, dataToProgram3, addressToProgram4, dataToProgram4) { writeToFlash (bank_address, 0x55) ; writeToFlash (addressToProgram1, dataToProgram1) ; /*see note (3) */
Write Address 2 & Data 2 (3)
writeToFlash (addressToProgram2, dataToProgram2) ; /*see note (3) */ writeToFlash (addressToProgram3, dataToProgram3) ; /*see note (3) */ writeToFlash (addressToProgram4, dataToProgram4) ; /*see note (3) */
Write Address 3 & Data 3 (3)
Write Address 4 & Data 4 (3)
/*Memory enters read status state after the Program command*/ do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/
Read Status Register
SR7 = 1 YES SR3 = 0 YES SR4 = 0 YES SR1 = 0 YES End
NO } while (status_register.b7== 0) ;
NO
VPP Invalid Error (1, 2)
if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ;
NO
Program Error (1, 2)
if (status_register.SR4==1) /*program error */ error_handler ( ) ;
NO
Program to Protected Block Error (1, 2)
if (status_register.SR==1) /*program to protect block error */ error_handler ( ) ;
}
AI06172
Note: 1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase operations. 3. Address 1 to Address 4 must be consecutive addresses differing only for bits A0 and A1.
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Figure 23. Program Suspend & Resume Flowchart and Pseudo Code
Start program_suspend_command ( ) { writeToFlash (any_address, 0xB0) ; writeToFlash (bank_address, 0x70) ; /* read status register to check if program has already completed */ Write 70h do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/
Write B0h
Read Status Register
SR7 = 1 YES SR2 = 1 YES Write FFh
NO
} while (status_register.SR7== 0) ;
NO
Program Complete
if (status_register.SR2==0) /*program completed */ { writeToFlash (bank_address, 0xFF) ; read_data ( ) ; /*read data from another block*/ /*The device returns to Read Array (as if program/erase suspend was not issued).*/
Read data from another address
} else { writeToFlash (bank_address, 0xFF) ; read_data ( ); /*read data from another address*/ writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume program*/ } } Read Data
Write D0h
Write FFh
Program Continues
AI06173
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Figure 24. Block Erase Flowchart and Pseudo Code
Start erase_command ( blockToErase ) { writeToFlash (bank_address, 0x20) ; writeToFlash (blockToErase, 0xD0) ; /* only A12-A20 are significannt */ /* Memory enters read status state after the Erase Command */
Write 20h
Write Block Address & D0h
Read Status Register
do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/
SR7 = 1
NO } while (status_register.SR7== 0) ;
YES SR3 = 0 YES SR4, SR5 = 1 NO SR5 = 0 YES SR1 = 0 YES End } NO Erase to Protected Block Error (1) if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ; NO Erase Error (1) if ( (status_register.SR5==1) ) /* erase error */ error_handler ( ) ; YES Command Sequence Error (1) if ( (status_register.SR4==1) && (status_register.SR5==1) ) /* command sequence error */ error_handler ( ) ; NO VPP Invalid Error (1) if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ;
AI06174
Note: If an error is found, the Status Register must be cleared before further Program/Erase operations.
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Figure 25. Erase Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
erase_suspend_command ( ) { writeToFlash (bank_address, 0xB0) ; writeToFlash (bank_address, 0x70) ; /* read status register to check if erase has already completed */
Write 70h
Read Status Register
do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/
SR7 = 1 YES SR6 = 1 YES Write FFh
NO
} while (status_register.SR7== 0) ;
NO
Erase Complete
if (status_register.SR6==0) /*erase completed */ { writeToFlash (bank_address, 0xFF) ;
read_data ( ) ; /*read data from another block*/ /*The device returns to Read Array (as if program/erase suspend was not issued).*/
Read data from another block or Program/Protection Program or Block Protect/Unprotect/Lock else
} { writeToFlash (bank_address, 0xFF) ; read_program_data ( ); /*read or program data from another address*/ writeToFlash (bank_address, 0xD0) ; /*write 0xD0 to resume erase*/ } }
Write D0h
Write FFh
Erase Continues
Read Data
AI06175
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Figure 26. Locking Operations Flowchart and Pseudo Code
Start
Write 60h
locking_operation_command (address, lock_operation) { writeToFlash (bank_address, 0x60) ; /*configuration setup*/ if (lock_operation==LOCK) /*to protect the block*/ writeToFlash (address, 0x01) ; else if (lock_operation==UNLOCK) /*to unprotect the block*/ writeToFlash (address, 0xD0) ; else if (lock_operation==LOCK-DOWN) /*to lock the block*/ writeToFlash (address, 0x2F) ; writeToFlash (bank_address, 0x90) ;
Write 01h, D0h or 2Fh
Write 90h
Read Block Lock States
Locking change confirmed? YES Write FFh
NO
if (readFlash (address) ! = locking_state_expected) error_handler () ; /*Check the locking state (see Read Block Signature table )*/
writeToFlash (bank_address, 0xFF) ; /*Reset to Read Array mode*/ }
End
AI06176
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Figure 27. Protection Register Program Flowchart and Pseudo Code
Start
Write C0h
protection_register_program_command (addressToProgram, dataToProgram) {: writeToFlash (bank_address, 0xC0) ;
Write Address & Data
writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/
Read Status Register
SR7 = 1 YES SR3 = 0 YES SR4 = 0 YES SR1 = 0 YES End
NO } while (status_register.SR7== 0) ;
NO
VPP Invalid Error (1, 2)
if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ;
NO
Program Error (1, 2)
if (status_register.SR4==1) /*program error */ error_handler ( ) ;
NO
Program to Protected Block Error (1, 2)
if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ;
}
AI06177
Note: 1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
APPENDIX D. COMMAND INTERFACE STATE TABLES Table 36. Command Interface States - Lock table
Current State of the Current Bank Current State of Other Bank Command Input to the Current Bank (and Next State of the Current Bank) Erase Confirm P/E Resume Unlock Confirm (D0h) Block Lock Clear Read Unlock Block lock Read Status Electronic Lock-Down Confirm CFI Query Register Signature setup (01h) (98h) (50h) (90h) Set CR setup (60h) Block LockDown Confirm (2Fh)
Mode
State
Others
Read Array (FFH)
Read Status Register (70h)
Set CR Confirm (03h)
Any State
Read
Array CFI Electronic Signature Status
SEE Read MODIFY Read Array Read Array Status Read Array TABLE Register Block Lock Unlock Lock-Down Error, Set CR Error Block lock Block Lock Unlock Unlock Lock-Down Lock-Down Error, Set Block CR Error Block Lock Unlock Lock-Down Error, Set CR Error Block Lock Unlock Lock-Down Error, Set CR Error
Read Elect. Sign. Block Lock Unlock Lock-Down Error, Set CR Error
Block Lock, Unlock, Read CFI Lock-Down, Read Array Read Array Read Array Set CR Setup Block Lock Block Lock Block Lock Block Lock Unlock Unlock Unlock Unlock Lock-Down Lock-Down Lock-Down Lock-Down Error, Set Error, Set Block Block CR Error CR Error
Setup Lock Unlock Lock-Down CR
Set CR
Any State
Error Lock SEE Read Unlock MODIFY Read Array Read Array Status Read Array Lock-Down TABLE Register Block Set CR SEE Read MODIFY Read Array Read Array Status Read Array TABLE Register
Read Elect. Sign.
Block LocK Unlock Read CFI Lock-Down Read Array Read Array Read Array Setup, Set CR Setup Block LocK Unlock Read CFI Lock-Down Read Array Read Array Read Array Setup, Set CR Setup Block LocK Unlock Read CFI Lock-Down Read Array Read Array Read Array Setup, Set CR Setup PS Read CFI Erase Error PS Read Array PS Read Array Erase Error PS Read Array Erase Error PS Read Array Erase Error
Any State
Protection Register
Done
Read Elect. Sign.
Any State
ProgramDouble/ Quadruple Program
Done
SEE Read MODIFY Read Array Read Array Status Read Array TABLE Register
Read Elect. Sign.
Setup Idle Erase Suspend Idle
Program Suspend
Read Array, CFI, Elect. Sign., Status Setup
SEE MODIFY TABLE Erase Error
PS Read Array Erase Error
Program (Busy) Erase (Busy)
PS Read Status Register Erase Error
PS Read Array Erase Error
PS Read Elect. Sign. Erase Error Read Elect. Sign.
Erase Error
Any State
Block/ Bank Erase
Error Done SEE Read MODIFY Read Array Read Array Status Read Array TABLE Register Erase (Busy) ES Read Array Erase (Busy) ES Read Array
Block LocK Unlock Read CFI Lock-Down Read Array Read Array Read Array Setup, Set CR Setup
Setup Busy Idle Program Suspend Erase Suspend Read Array, CFI, Elect. Sign., Status SEE MODIFY TABLE ES Read Array
ES Read Status Register
ES Read Array
ES Read Elect. Sign.
ES Read CFI
Block LocK Unlock ES Read Lock-Down Array Setup, Set CR Setup
ES Read Array
ES Read Array
Note: PS = Program Suspend, ES = Erase Suspend.
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Table 37. Command Interface States - Modify Table
Current State of the Other Bank Setup Busy Idle Erase Suspend Program Suspend Setup Busy Idle Erase Suspend Program Suspend Idle Setup Busy Idle Erase Suspend Program Suspend Any State Idle Setup Busy Idle Erase Suspend Program Suspend Setup Idle Erase Suspend Program Double/ Quadruple Word Program Lock Unlock Lock-Down CR Read Current State of the Current Bank Mode State Others Command Input to the Current Bank (and Next State of the Current Bank) Program Setup (10h/40h) Read Array Array, CFI, Electronic Signature, Status Register SEE LOCK TABLE Program setup Read Array Read Array Error, Lock Unlock Lock-Down Block, Set CR Setup Busy Protection Register SEE LOCK TABLE Block Erase Setup (20h) Read Array Block Erase Setup Read Array Read Array Double/ Protection Quadruple Program-Erase Register Suspend (B0h) Program Setup Program Setup (30h/55h) (C0h) Read Array Protection Register Setup Read Array Read Array Double/ Quadruple Program Setup Read Array Read Array Double/ Quadruple Program Setup Read Array Bank Erase Setup (80h) Read Array Bank Erase Setup Read Array
Read Array Block Erase Setup Read Array Read Array
Read Array Protection Register Setup Read Array
Read Array Bank Erase Setup Read Array
Program setup Read Array
Protection Protection Protection Protection Protection Protection Protection Register (Busy) Register (Busy) Register (Busy) Register (Busy) Register (Busy) Register (Busy) Register (Busy) Read Array Read Array Block Erase Setup Read Array Read Array Protection Register Setup Read Array Read Array Double/ Quadruple Program Setup Read Array Read Array Bank Erase Setup Read Array
Done
SEE LOCK TABLE
Program Setup Read Array
Read Array
Setup Busy
Program (Busy) Program (Busy) Program (Busy) Program (Busy) PS Read Status Program (Busy) Program (Busy) Program (Busy) Register Read Array Read Array Block Erase Setup Read Array Read Array Read Array Protection Register Setup Read Array Read Array Double/ Quadruple Program Setup Read Array Read Array Bank Erase Setup Read Array
Done
SEE LOCK TABLE
Program Setup Read Array
Program Suspend
Read Array, CFI, Elect. Sign., Status Register Setup Busy
SEE LOCK TABLE SEE LOCK TABLE Erase (Busy)
PS Read Array PS Read Array PS Read Array PS Read Array PS Read Array PS Read Array
Idle Setup Busy Idle Program Suspend
Block/ Bank Erase
Erase Error Erase (Busy) ES Read Array
Erase Error
Erase Error
Erase Error Erase (Busy)
Erase Error Erase (Busy) ES Read Array
Erase Error Erase (Busy)
ES Read Status Erase (Busy) Register
Erase Suspend
Read Array, CFI, Elect. Sign., Status Register
SEE LOCK TABLE
Program Setup ES Read Array ES Read Array ES Read Array ES Read Array
Double/ ES Read Array Quadruple Program Setup ES Read Array
Note: PS = Program Suspend, ES = Erase Suspend.
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
REVISION HISTORY Table 38. Document Revision History
Date November 2000 12/20/00 Version -01 -02 First Issue Protection/Security clarification Memory Map diagram clarification (Figure 4) Single Synchronous Read clarification (Figure 6) Identifier Codes clarification (Table 6) X-Latency configuration clarification CFI Query Identification String change (Table 31) Synchronous Burst Read Waveforms change (Figure 12) Reset AC Characteristics clarification (Table 24) Program Time clarification (Table ) Reset AC Characteristics clarification (Table 24) Reset AC Waveforms diagram change (Figure 1) Document type: from Target Specification to Product Preview Read Status Register clarification Read Electronic Signature clarification Protection Register Program clarification Write Configuration Register clarification Wait Configuration Sequence change (Figure 7) CFI Query System Interface clarification (Table 32) CFI Device Geometry change (Table 33) Asynchronous Read AC Waveforms change (Figure 10) Page Read AC Waveforms added (Figure 11) Write AC Waveforms W Contr. and E Contr. change (Figure 14, 15) Reset and Power-up AC Characteristics and Waveform change (Table 24, Figure 1) TFBGA Package Mechanical Data and Outline added (Table 25, Figure 17) TFBGA Connections change X-Latency Configuration Sequence change Reset and Power-up AC Characteristics clarification VDDQ clarification Complete rewrite and restructure 85ns speed class added, document classified as Preliminary Data Part numbers M58CR064P/Q added. CFI information clarified: Table 31,data modified at Offset 13h. Table 32, data modified at Offsets 20h, 23h, 24h and 25h. Table 35, Offset addresses modified. DC Characteristics table modified, Program, Erase Times and Program, Erase Endurance Cycles table modified. Document changed to new structure Revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot. (revision version 09 equals 9.0). Document status changed from Preliminary Data to Datasheet. Minimum VDD and VDDQ supply voltages for 85ns speed class changed to 1.8V in Table16, Operating and AC Measurement Conditions. Revision Details
1/08/01 3/02/01
-03 -04
4/05/01
-05
23-Jul-2001 23-Oct-2001 15-Mar-2002
-06 -07 -08
23-May-2002 27-Aug-2002
-09 9.1
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Date 24-Feb-2003 Version 9.2 Revision Details Revision History moved to end of document. 90ns Speed Class added. Bank Erase Command moved to Factory Program Commands section. Bank Erase cycles limited to 100 per Block. WAIT signal modified in Figure 7, Wait Configuration Example. WAIT behavior modified. Burst sequence in wrapped configuration and Burst sequence start specified in Synchronous Burst Read Mode paragraph. Erase replaced by Block Erase in Tables 11 and 12, Dual Operations allowed in Other Bank and in Same Bank, respectively. Latch signal corrected in Figure 11, Asynchronous Page Read AC Waveforms. Daisy Chain added. VDD and VDDQ minimum values changed for 90ns speed class in Table 16, Operating and AC Measurement Conditions. Minor text changes.
06-Jun-2003
9.3
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2003 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. www.st.com
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